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| fujitsu microelectronics proprietary and confidential MB86R01 data sheet july, 2009 the 1.4 edition
i fujitsu microelectronics proprietary and confidential MB86R01 data sheet trademarks arm is a registered trademark of arm limited in uk, usa and taiwan. arm is a trademark of arm limited in japan and korea. arm926ej-s and etm9 are trademarks of arm limited. ? the contents of this document are subject to change without notice. customers are advised to consult with sales representatives before ordering. ? the information, such as descriptions of function an d application circuit exampl es, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu microelectronics device; fujitsu microelectronics does not warran t proper oper ation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu microelectronics assumes no liability for any damages whatsoev er arising out of the use of the information. ? any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu microelectronics or any third party or does fujitsu microelectronics warrant non-infring ement of any third-party's inte llectual property right or other right by using such information. fujitsu microelectronics assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. ? the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air tr affic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater an d artificial satellite). please note that fujitsu microelectronics will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. ? any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. ? exportation/release of any product s described in this document may require necessary procedures in accordance with the regulations of the foreign exchange and foreign trade control law of japan and/or us export control laws. ? the company names and brand names herein are the trad emarks or registered trad emarks of their respective owners. all rights reserved, copyright fujits u microelectronics limited 2007 - 2009 ii fujitsu microelectronics proprietary and confidential MB86R01 data sheet revision history date ver. contents 2007/07/12 1.0 newly issued 2007/08/20 1.1 8.3.1. recommende d power on/off sequence ? revised the last line of descript ion (pll reference clock part) 8.4.3. adc ? revised value of table 8-16 ? revised and deleted descriptive content of note ? revised footnote (*2) of table 8-17 8.4.4. i 2 c bus fast mode i/o ? revised table 8-18 and footnote ? deleted footnote (*3) 8.5.9. i 2 c bus timing ? revised footnote (*2) of table 8-37 8.5.12. mlb signal timing ? revised mlb to medialb ? revised footnote of table 8-42, 8-45 2007/11/09 1.2 4. function list ? revised contents of the list 6. pin assignment ? revised figures in 1-8/1-9 pages ? added "top view" statement 7.1. pin multiplex ? revised description of note ? added mode setting description to pin multiplex group #1 ~ #5 ? revised table of pin multiplex group #2 and #4 7.2.4. usb 2.0 host/function related pin ? revised description of usb_ext12k pin 7.2.5. external interrupt controller related pin ? revised title 7.2.12. a/d converter related pin ? revised pin name: ad_avd0 ad_avd, ad_avs1 ad_avs 7.2.24. unused pin ? added this section 7.2.25. unused pin with pin multi plex function in the duplex case ? added this section 8.4.2. ddr2sdram if i/o (sstl_18) ? revised table 8-12 8.5.1. memory controller signal timing ? revised table 8-21 ? revised figure 8-8 and 8-9 ? added figure 8-10, 8-11, and 8-12 8.5.6.2. input signal ? revised figure 8-23 2008/02/07 1.3 6. pin assignment ? revised figure and table 7.2.2. ide66 related pin ? revised type ? revised status pin after reset 7.2.3. sd memory controller related pin ? unified sd_dat[0] and sd_dat[3:1] 7.2.7. can related pin ? revised type iii fujitsu microelectronics proprietary and confidential MB86R01 data sheet date ver. contents 2008/02/07 1.3 7.2.8. i2s related pin ? revised type ? revised status pin after reset 7.2.10. spi related pin ? revised type 7.2.11. pwm related pin ? revised type ? added comment 7.2.13. ddr2 related pin ? revised resistance value of *2 7.2.15. video captured related pin ? revised type ? added comment 7.2.18. ice related pin ? revised status pin after reset of xsrst 7.2.20. etm related pin ? revised pin name in description column of traceclk 7.2.22. medialb related pin ? revised pin name ? revised type 7.2.24. unused pin ? revised process ? deleted bigend ? revised pin name of b17, b16, c17, c16, and d16 7.2.25. unused pin with pin mu ltiplex function in the duplex case ? revised process 8.1. maximum ratings ? revised table 8-1 2009/07/07 1.4 7.2.14. display related pin ? added note 8.1. maximum ratings ? revised table 8-1 8.3.2. power on reset ? revised figure 8-3 ? revised description 8.5.5.1. clock ? revised table 8-28 8.5.7. i2s signal timing ? revised table 8-34 and 8-35 8.5.10. spi signal timing ? revised table 8-38 iv fujitsu microelectronics proprietary and confidential MB86R01 data sheet contents 1. outline ................................................................................................................. 1 2. feature................................................................................................................. 1 3. block di agram..................................................................................................... 2 4. function list ........................................................................................................ 4 5. package dime nsion ............................................................................................ 6 6. pin assignm ent ................................................................................................... 7 7. pin func tion....................................................................................................... 10 7.1. pin multip lex.................................................................................................................. ....................... 10 7.2. pin function ................................................................................................................... ....................... 16 7.2.1. external bus inte rface related pin............................................................................................. ..... 17 7.2.2. ide66 related pin .............................................................................................................. ............ 17 7.2.3. sd memory controller related pin............................................................................................... .. 18 7.2.4. usb 2.0 host/func tion relate d pin .............................................................................................. . 18 7.2.5. external interrupt co ntroller related pin ...................................................................................... .. 18 7.2.6. uart relate d pin ............................................................................................................... ........... 19 7.2.7. can related pin ................................................................................................................ ............ 19 7.2.8. i2s related pin ................................................................................................................ ............... 19 7.2.9. i 2 c related pin .................................................................................................................. ............. 20 7.2.10. spi related pin ................................................................................................................ ............... 20 7.2.11. pwm relate d pin ................................................................................................................ ........... 20 7.2.12. a/d converter related pin...................................................................................................... ........ 20 7.2.13. ddr2 related pin ............................................................................................................... ........... 21 7.2.14. display related pin ............................................................................................................ ........ 22 7.2.15. video capture related pin...................................................................................................... ......... 23 7.2.16. system related pin ............................................................................................................. ............ 23 7.2.17. jtag rela ted pin ............................................................................................................... ............ 23 7.2.18. ice relate d pin ................................................................................................................ .............. 24 7.2.19. multiplex setting related pin .................................................................................................. ....... 24 7.2.20. etm relate d pin ................................................................................................................ ............ 24 7.2.21. power supply related pin ....................................................................................................... ........ 24 7.2.22. medialb rela ted pin............................................................................................................ .......... 25 7.2.23. gpio rela ted pin ............................................................................................................... ............ 25 7.2.24. unused pin ..................................................................................................................... ............... 26 7.2.25. unused pin with pin multiplex function in the duplex case .......................................................... 34 8. electrical char acteristics................................................................................. 35 8.1. maximum ratings................................................................................................................ ................. 35 v fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.2. recommended opera ting conditions ............................................................................................... .... 37 8.3. precautions at power on ........................................................................................................ ............... 38 8.3.1. recommended power on /off sequence ....................................................................................... 38 8.3.2. power on reset................................................................................................................. ............ 39 8.4. dc charact eristics ............................................................................................................. ................... 40 8.4.1. 3.3v standard cmos i/o ......................................................................................................... .... 40 8.4.1.1. 3.3v standard cmos i/o v-i char acteristic (driving capability 1).................................... 41 8.4.1.2. 3.3v standard cmos i/o v-i char acteristic (driving capability 2).................................... 42 8.4.1.3. 3.3v standard cmos i/o v-i char acteristics (driving capab ility 3) .................................. 43 8.4.2. ddr2sdram if i/o (sstl_18) ................................................................................................ 44 8.4.3. adc .............................................................................................................................................. 46 8.4.4. i 2 c bus fast mode i/o .................................................................................................................. 47 8.4.4.1. i 2 c io v-1 charact eristic figure ........................................................................................... 48 8.4.5. usb2.0......................................................................................................................... ................. 49 8.5. ac characteristic .............................................................................................................. ........ 50 8.5.1. memory controller signal timing ................................................................................................ 50 8.5.2. ddr2sdram if.......................................................................................................................... 54 8.5.2.1. ddr2sdram if timing diagram ...................................................................................... 55 8.5.3. gpio signal timing............................................................................................................. ......... 58 8.5.4. pwm signal timing .............................................................................................................. ....... 59 8.5.4.1. output signal .................................................................................................................. ...... 59 8.5.5. gdc display si gnal timing ...................................................................................................... ... 60 8.5.5.1. clock .......................................................................................................................... ........... 60 8.5.5.2. input si gnal ................................................................................................................... ........ 60 8.5.5.3. output signal .................................................................................................................. ...... 61 8.5.6. gdc video captur e signal timing............................................................................................... 63 8.5.6.1. clock .......................................................................................................................... ........... 63 8.5.6.2. input si gnal ................................................................................................................... ........ 63 8.5.7. i2s signal timing .............................................................................................................. ........... 65 8.5.8. uart signal timing ............................................................................................................. ....... 67 8.5.9. i 2 c bus timing................................................................................................................... ........... 68 8.5.10. spi signal timing .............................................................................................................. ........... 69 8.5.11. can signal timing.............................................................................................................. ......... 70 8.5.12. medialb signa l timing.......................................................................................................... ...... 71 8.5.12.1. medialb ac spec type a .................................................................................................... 71 8.5.12.1.1. clock .......................................................................................................................... ... 71 8.5.12.1.2. input si gnal ................................................................................................................... 71 8.5.12.1.3. output signal................................................................................................................. 71 8.5.12.2. medialb ac spec type b .................................................................................................... 72 8.5.12.2.1. clock .......................................................................................................................... ... 72 8.5.12.2.2. input si gnal ................................................................................................................... 72 8.5.12.2.3. output signal ................................................................................................................. 72 8.5.13. usb2.0 sign al timing ........................................................................................................... ....... 74 8.5.14. ide66 signal timing .................................................................................................................... 76 8.5.14.1. ide pio timing .................................................................................................................... 76 8.5.14.2. ide ultra dma timing ........................................................................................................ 78 8.5.15. sd signal timing............................................................................................................... ........... 80 8.5.15.1. clock .......................................................................................................................... ........... 80 8.5.15.2. input/output signal ............................................................................................................ ... 80 8.5.16. etm9 trace port si gnal timing .................................................................................................. . 81 8.5.17. exirc signal timing ............................................................................................................ ....... 82 1 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 1. outline MB86R01 is lsi product for the graphics applications with arm limited's cpu arm926ej-s and fujitsu's gdc mb86296 as its core. this product contains peripheral i/o resources, such as in-vehicle lan, hdd, and usb; therefore only a single chip of MB86R01 controls main graphics application system which usually requires 2 chips (cpu and gdc.) 2. feature ? cmos 90nm technology ? package: pbga484 ? power-supply voltage: (io: 3.3 0.3v, core: 1.2 0.1v, ddr2: 1.8 0.1v) ? operation frequency: 333mhz (cpu), 83mhz (ahb), 41.5mhz (apb) ? cpu core ? arm926ej-s ? 16kb instruction cache/16kb data cache ? 16kb itcm/16kb dtcm ? etm9cs single and jtag ice interface ? java acceleration (jazelle technology) ? bus architecture ? multi-layer ahb bus architecture ? interrupt ? built-in sram ? clock/reset control function ? remap/boot control function ? 16 bit external bus interface with decoding engine ? 32 bit ddr2 memory interface (target: 166mhz: 333mbps) ? graphics display controller ? 2d/3d rendering engine of fujitsu mb86296 ? rgb66 video output 1ch (extensible to rgb888 with using option i/o) ? itu rbt-656 video capture 1ch (extensible to rgb666 with using option i/o) ? usb 2.0 host (hs/fs protocols) 1ch ? ide66 (ata/atapi-5) 1ch ? sd memory interface (sdio/cprm: unsupported) 1ch ? 10 bit a/d converter (1ms/s) 2ch ? i 2 c (i/o voltage: 3.3v) 2ch ? uart 3ch (extensible up to 6ch with using option i/o) ? 32/16 bit timer 2ch ? dmac 8ch option i/o (with pin multiplex) ? rgb666 video output is extensible to 2ch ? video capture is extensible to 2ch ? medialb (most50) 1ch is addable ? can (i/o voltage: 3.3v) 2ch is addable ? usb 2.0 function (hs/fs pr otocols) is switchable (usb 2.0 function and usb 2.0 host are accessed exclusively) ? gpio is addable up to 24 ? spi 1ch is addable ? pwm 2ch is addable 2 fujitsu microelectronics proprietary and confidential MB86R01 data sheet ? i2s is addable up to 3ch ? the number of uart channel is extensible up to 6ch ? the data width in the external bus interface is extensible to 32 bit 3. block diagram figure 3-1 shows block diagram of MB86R01. crg m1-0 m1-1 s1-00 m1-2 s1-01 master no. slave no. dmac 8ch s1-04 rbc gpio 24ch extirc 4ch uart 4 32bit timer 2ch i-tcm 16kb etm9cssingle s1-12 s1-05 s1-02 usb2.0 host m1-4 sram 32kb s1-10 medialb ide66 s1-08 ccpb s1-11 boot rom 32kb uart 2 s1-15 d i i2s_1 sdmc i2s_0 jtag_sel chip_jtag s2-00 s1-13 s1-14 irc irc 2 s1-07 usb2.0 function phy m1-5 usb2.0 function dmac s2-02 s1-03 disp ddr2 controller mbus2axi mbus2axi disp cap cap draw & geo host if ahb2axi s2-03 m1-6 ide66 dmac m2-0 m1-7 s1-09 s2-01 m1-8 wrapper external bus i/f hbus2axi sram 32kb s1-06 i2s_2 s2-04 can 2 pwm 2 uart 2 i2c 2 adc 4 adc 2 i2c 2 can 2 pwm 2ch spi 1 ccnt uart 4 uart 2 wrapper d-tcm 16kb i-cache 16kb d-cache 16kb jtag if figure 3-1 block diagram of MB86R01 cpu core this is cpu core block of arm926ej-s which is connected to each i/o through ahb bus in lsi. instruction (i)/data (d) function as a separate bus master for harvard architecture. gdc_top this is mb86296 compatible gdc which has 2 functions: ahb slave function writes required display list for drawing to gdc with having cpu or dma controller as master, and axi master function reads display list arranged in ddr2 memory with having gdc as master. axi bus this bus bridges main memory and internal res ource. following four bu s masters are connected. ? ahb1: each bus master of ahb bus such as cpu and dma controller ? hbus: host if on gdc ? draw & geo: draw (2d/3d drawing) and geo (geometry engine) on gdc ? mbus: disp (display controller) and cap (video capture) on gdc 3 fujitsu microelectronics proprietary and confidential MB86R01 data sheet ahb1 bus following resources are connected. ? cpu core: bus masters of instruction (i)/data (d) ? gdc: gdc register part ? ahb2axi: axi port for main memory access ? ccpb: encrypted rom decoding block ? external bus i/f: external bus in terface (connected through ccpb) ? sram: general purpose internal sram 32kb 2 ? dmac: general purpose dma 8ch it operates as bus master at data transfer ? boot rom: built-in boot rom ? i2s_0/1/2: serial audio controller 3ch ? usb 2.0 function dmac: usb function dmac it operates as bus master at data transfer ? usb2.0 host: it operates as usb2.0 ehci, usb1.1 ohci bus masters ? ide66/ide66dmac: register part of ide host controller and built-in dmac the dmac part operates as bus master at data transfer ? mlb: medialb controller ? ahb2 ? apbbrg0/1/2: ahb-apb bridge circuit 3ch ahb2 bus ? ccpb: encrypted rom decoding block ? usb 2.0 function: usb 2.0 function controller's register part ? usb 2.0 host: usb 2.0 host controller's register part ? sdmc: sd memory controller ? ddr2 controller: ddr2 controller's register part apb_top_0 this block bridges between apbbrg0 bus and ahb1 bus, and following low-speed peripheral resources are connected. ? interrupt controller (irc) 2ch ? external interrupt controller (extirc) ? clock reset generator (crg) ? uart (ch0 and ch1) 2ch ? remap boot controller (rbc) ? 32 bit general-purpose timer (32 bit timer) 2ch apb_top_1 this block bridges between apbbrg1 bus and ahb1 bus, and following low-speed peripheral resources are connected. ? i 2 c controller 2ch ? can controller 2ch ? uart (ch2 and ch3) 2ch ? a/d converter (adc) 2ch apb_top_2 this block bridges between apbbrg2 bus and ahb1 bus, and following low-speed peripheral resources are connected. ? pwm controller (pwm) ? spi controller (spi) ? ccnt ? uart (ch4 and ch5) 2ch 4 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 4. function list function list of MB86R01 is shown below. function outline cpu core ? arm926ej-s tm processor core ? core operation frequency: 333mhz ? 16kb instruction cache ? 16kb data cache ? tightly-coupled memory for 16kb instruction (itcm) ? tightly-coupled memory for 16kb data (dtcm) ? etm9cs single and jtag ice debugging interface ? java acceleration (jazelle technology) bus architecture ? multilayer ahb bus architecture (software interrupt) ? speeding up data transfer between main memo ry and each bus master with 64 bit axi bus interrupt ? high-speed interrupt 1ch h (soft interrupt) ? normal interrupt 64ch (external interrupt 4ch + built-in internal interrupt 60ch) ? up to 16 interrupt levels are settable by channel clock ? pll multiplication: selectable from 15 ~ 49 ? operation frequency: 333mhz (cpu), 83mhz (ahb), 41.5mhz (apb) ? low power consumption mode (clock to arm and module is stoppable) reset ? hardware reset, software reset, and watchdog reset remap ? rom area is able to be mapping to built-in sram area external bus interface ? three chip select signals ? provided 32m byte address space in each chip select ? supported 16/32 bit width sram/flash rom connection ? programmable wei ght controller ? encrypted rom compound engine ddr2 controller ? supported ddr2sdram (ddr2-400) ? connectable capacity: 256 ~ 512m bit 2 or 256 ~ 512m bit 1 ? i/o width: selectable from 16/ 32 bit ? max. transfer rate: 166mhz/333mbps built-in sram ? mounted general purpose sram of 32kb 2 (32 bit bus) dmac ? ahb connection 8ch ? transfer mode: block, burst, and demand timer ? 32/16 bit programmable 2 channels gpio (*2) ? max. 24 is usable ? interrupt function pwm (*2) ? built-in 2 channels ? duty ratio and phase are configurable a/d converter ? 10 bit successive approxima tion type a/d converter 2ch ? sampling rate: 648ks/s (max. sampling plate) ? nonlinearity error: 2.0lsb (max.) 5 fujitsu microelectronics proprietary and confidential MB86R01 data sheet function outline gdc (*1) ? display controller rgb666 or rgb888 output max. resolution is 1024 768 max. 6 layered display max. 2 screen output ? digital video capture function bt.601, bt.656, and rgb666 max. 2 inputs ? geometry engine (mb86296 compa tible display list is usable) ? 2d/3d drawing function (mb86296 comp atible display list is usable) i2s (*2) ? audio output 3ch (l/r)/audio input 3ch (l/r) ? supported three-wire serial (i2s, msb-justified) and serial pcm data transfer interface ? master/slave operations are selectable ? resolution capability: max. 32 bit/sample uart (*2) ? max. 6 channels (dedicated channel: 3ch, option: 3ch) ? 1 channel: capable of input/output cts/rts signals ? 8 bit pre-scaler for baud rate clock generation ? enabled dma transfer i 2 c ? 3.3v pin 2ch ? supported standard mode (max. 100kbps)/high-speed mode (max. 400kbps) spi (*2) ? full duplex/synchronous transmission ? transfer data length: 1 bit unit (max . 32 bit) (programmable setting) can (*2) ? mounted bosch c_can module 2ch ? conformed to can protocol version 2.0 part a and b ? i/o voltage: 3.3v medialb (*2) ? 16 channels ? medialb clock speed: 256fs/512fs/1024fs ? built-in 9k bit channel buffer usb (*2) ? usb 2.0 compliant host/function controller 1ch (pin multiplex) ? hs/fs protocol support (supported vbus and isochronous transfer) ide (*2) ? supported ata/atapi-5 ? equipped 1 channel ? supported primary ide channel ? equipped transmission fifo buffer (512 byte 2) and reception fifo buffer (512 byte 2) for the ultra dma transfer ? unsupported single word dma and multiword dma sdmc ? conformed to sd memory card physical layer specification 1.0 ? equipped 1 channel ? supported sd memory card and multimedia card ? unsupported spi mode, sd io mode, and cprm ccnt ? mode selection of multiplex pin group 2 and 4 ? software reset control ? axi interconnection control (priority and wait setting) jtag ? conformed to ieieee1149.1 (ieee standard test access port and boundary-scan architecture) ? supported jtag ice connection *1: number of layer of simultaneous display and number of output display as well as capture input for displaying in high resolution may be restricted due to data su pply capacity of graphics memory (ddr2 controller). *2: a part of external pin functions of this lsi is multip lexed. max. number of usable channel is limited by pin multiplex function setting. 6 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 5. package dimension package dimension of MB86R01 is shown below. 7 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 6. pin assignment pin assignment of MB86R01 is shown below. (top view) 1234567891011121314151617181920212223242526 a 1100999897969594939291908988878685848382818079787776 b 2 101 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 75 c 3 102 193 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 169 74 d 4 103 194 277 352 351 350 349 348 347 346 345 344 343 342 341 340 339 338 337 336 335 334 255 168 73 e 5 104 195 278 353 420 419 418 417 416 415 414 413 412 411 410 409 408 407 406 405 404 333 254 167 72 f 6 105 196 279 354 403 332 253 166 71 g 7 106 197 280 355 402 331 252 165 70 h 8 107 198 281 356 401 330 251 164 69 j 9 108 199 282 357 400 329 250 163 68 k 10 109 200 283 358 421 448 447 446 445 444 443 442 399 328 249 162 67 l 11 110 201 284 359 422 449 468 467 466 465 464 441 398 327 248 161 66 m 12 111 202 285 360 423 450 469 480 479 478 463 440 397 326 247 160 65 n 13 112 203 286 361 424 451 470 481 484 477 462 439 396 325 246 159 64 p 14 113 204 287 362 425 452 471 482 483 476 461 438 395 324 245 158 63 r 15 114 205 288 363 426 453 472 473 474 475 460 437 394 323 244 157 62 t 16 115 206 289 364 427 454 455 456 457 458 459 436 393 322 243 156 61 u 17 116 207 290 365 428 429 430 431 432 433 434 435 392 321 242 155 60 v 18 117 208 291 366 391 320 241 154 59 w 19 118 209 292 367 390 319 240 153 58 y 20 119 210 293 368 389 318 239 152 57 aa 21 120 211 294 369 388 317 238 151 56 ab 22 121 212 295 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 316 237 150 55 ac 23 122 213 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 236 149 54 ad 24 123 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 148 53 ae 25 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 52 af 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 8 fujitsu microelectronics proprietary and confidential MB86R01 data sheet (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 a vss vss dclko0 vss dclkin0 doutg0 [6] doutg0 [2] doutb0 [4] xsrst trace data[3] xrst pllvss pllvdd tdo vss clk mem xrd vss mem ea[20] mem ea[16] mem ea[12] mem ea[8] mem ea[4] mem ea[1] vss vss b vss de0 hsync0 vdde doutr0 [4] doutg0 [7] doutg0 [3] doutb0 [5] xtrst trace ctl trace data[0] tms vinithi cripm3 vdde mem xcs[4] mem xwr[1] mem ea[23] mem ea[19] mem ea[15] mem ea[11] mem ea[7] mem ea[3] mem ed[15] mem ed[14] vss c doutb1 [2] gv0 vsync0 doutr0 [7] doutr0 [5] doutr0 [2] doutg0 [4] doutb0 [6] doutb0 [2] trace clk trace data[1] jtagsel tck cripm2 cripm0 mem xcs[2] mem xwr[0] mem ea[22] mem ea[18] mem ea[14] mem ea[ 10] mem ea[6] mem ea[2] mem ed[13] mem ed[12] mem ed[11] d doutb1 [6] doutb1 [5] doutb1 [4] doutb1 [3] doutr0 [6] doutr0 [3] doutg0 [5] doutb0 [7] doutb0 [3] rtck trace data[2] p lltdtrs t tdi cripm1 mem rdy mem xcs[0] mem ea[24] mem ea[21] mem ea[17] mem ea[13] mem ea[9] mem ea[5] mem ed[10] mem ed[9] mem ed[8] mem ed[7] e doutg1 [4] doutg1 [3] doutg1 [2] doutb1 [7] vdde vss vss vdde vdde vddi vddi vss vss vdde vdde vddi vddi vss vss vdde vdde v ddi mem ed[6] mem ed[5] mem ed[4] mem ed[3] f doutr1 [2] doutg1 [7] doutg1 [6] doutg1 [5] vdde vddi mem ed[2] mem ed[1] mem ed[0] vss g dclkin 1 doutr1 [5] doutr1 [4] doutr1 [3] vddi vss mdq[30] mdm[3] mdq[31] mdqs p[3] h vss vdde doutr1 [7] doutr1 [6] vddi vss mdq[25] mdq[28] mdq[24] mdqs n[3] j dclko1 gv1 vsync1 hsync1 vss ddrvde mdq[27] mdq[26] mdq[29] vss k vin0 [5] vin0 [6] vin0 [7] de1 vss vddi vdde vdde vddi vddi vdde vdde vddi ddrvde mdm[2] mdq[23] vr ef1 mdqs p[2] l vin0 [1] vin0 [2] vin0 [3] vin0 [4] vdde vddi vss vss vss vss vss vss vddi dq22 mdq[20] mdq[17] mdq[16] mdqs n[2] m cclk0 vdde vin vsync0 vin0 [0] vdde vdde vss vss vss vss vss vss ddrvde vss mdq[19] mdq[18] mdq[21] vss n vss vinfid0 vin hsync0 vddi vddi vdde vss vss vss vss vss vss ddrvde vddi odt vss ddrvde mckp p usb avsp usb avdp usb avsf1 usb_ avsb usb avdb vddi vss vss vss vss vss vss vddi vddi ocd vss ddrvde mckn r usb hsdp usb fsdp usb avdf1 usb avsf2 usb ext12k vddi vss vss vss vss vss vss vddi vss mdq[14] mdm[1] mdq[15] vss t usb hsdm usb fsdm usb avsf2 usb avsf2 usb avsf2 vdde vss vss vss vss vss vss ddrvde ddrvde mdq[12] mdq[9] mdq[8] mdqs p[1] u usb avsf2 usb avsf2 usb avdf2 vss vddi vdde vddi vddi vdde vdde vddi vddi ddrvde ddrvde mdq[11] mdq[10] mdq[13] mdqs n[1] v usb cryck48 usb mode vin1 [7] vss vddi mdq[6] mdm[0] mdq[7] vref0 vss w vin1 [6 ] vin1 [5] vin1 [4] vin1 [3] vdde vss mdq[4] mdq[1] mdq[0 mdqs p[0] y vss vin1 [2] vin1 [1] vin1 [0] vdde vss mdq[3] mdq[5] mdq[2] mdqs n[0] aa cclk1 vdde vin vsync1 vin hsync1 vss ddrvde mcas mras mcke vss ab vinfid1 i2s sdo2 i2s sdi2 i2s ws2 vss vdde vdde vddi vddi vss vss vdde ad vrl0 ad vrl1 vss vss vss vdde vdde vddi vddi ddrvde mcs mwe mba[0] mba[1] ac i2s sck2 pwm_o1 ide diordy ide dintrq ide dd[15] ide dd[11] ide dd[7] ide dd[3] ide da[2] ide xdiow mpx mode_1 [0] test mode[0] ad vr0 ad vr1 vdde uart sin2 sd clk sd dat[3] vpd int_a [2] ddrtype odtcon t ma[0] ma[2] ma[10] ma[1] ad i2s eclk2 pwm_o0 ide xcblid ide ddmarq ide dd[14] ide dd[10] ide dd[6] ide dd[2] ide da[1] ide xdior mpx mode_1 [1] pll bypass ad vin0 ad vin1 vdde uart sout2 sd cmd sd dat[2] usb prtpwr i2c sda0 int_a [1] test mode[2] ma[9] ma[6] ma[5] ma[3] ae vss vss ide xdasp ide xddmac k ide dd[13] ide dd[9] ide dd[5] ide dd[1] ide da[0] ide xdcs[0] mpx mode_5 [0] bigend ad vrh0 ad vrh1 uart xrts0 uart xcts0 uart sout1 sd dat[1] sd xmcd i2c scl0 int_a [3] mcke start ma[13] ma[4] ma[11] ma[7] af vss vss ide xiocs16 ide dreset ide dd[12] ide dd[8] ide dd[4] id e dd[0] ide csel ide xdcs[1] mpx mode_5 [1] test mode[1] ad avd ad avs uart sout0 uart sin0 uart sin1 sd dat[0] sd wp i2c scl1 i2c sda1 int_a [0] ma[8] ma[12] vss vss 9 fujitsu microelectronics proprietary and confidential MB86R01 data sheet pin assignment table pin no jedec pin name pin no jedec pin name pin no jedec pin name pin no jedec pin name pin no jedec pin name 1 a1 vss 101 b2 de0 201 l3 vin0[3] 301 ac9 ide_da[2] 401 h22 vss 2 b1 vss 102 c2 gv0 202 m3 vinvsync0 302 ac10 ide_xdiow 402 g22 vss 3 c1 doutb1[2] 103 d2 doutb1[5] 203 n3 vinhsync0 303 ac11 mpx_mode_1[0] 403 f22 vddi 4 d1 doutb1[6] 104 e2 doutg1[3] 204 p3 usb_avsf1 304 ac12 testmode[0] 404 e2 2 vddi 5 e1 doutg1[4] 105 f2 doutg1[7] 205 r3 usb_avdf1 305 ac13 ad_vr0 405 e21 vdde 6 f1 doutr1[2] 106 g2 doutr1[5] 206 t3 usb_avsf2 306 ac14 ad_vr1 406 e20 vdde 7 g1 dclkin1 107 h2 vdde 207 u3 usb_avdf2 307 ac15 vdde 407 e19 vss 8 h1 vss 108 j2 gv1 208 v3 vin1[7] 308 ac16 uart_sin2 408 e18 vss 9 j1 dclko1 109 k2 vin0[6] 209 w3 vin1[4] 309 ac17 sd_clk 409 e17 vddi 10 k1 vin0[5] 110 l2 vin0[2] 210 y3 vin1[1] 310 ac18 sd_dat[3] 410 e16 vddi 11 l1 vin0[1] 111 m2 vdde 211 aa3 vinvsync1 311 ac19 vpd 411 e15 vdde 12 m1 cclk0 112 n2 vinfid0 212 ab3 i2s_sdi2 312 ac20 int_a[2] 412 e14 vdde 13 n1 vss 113 p2 usb_avdp 213 ac3 ide_diordy 313 ac21 ddrtype 413 e13 vss 14 p1 usb_avsp 114 r2 usb_fsdp 214 ad3 ide_xcblid 314 ac22 odtcont 414 e12 vs s 15 r1 usb_hsdp 115 t2 usb_fsdm 215 ad4 ide_ddmarq 315 ac23 ma[0] 415 e11 vddi 16 t1 usb_hsdm 116 u2 usb_avsf2 216 ad5 ide_dd[14] 316 ab23 mcs 416 e10 vddi 17 u1 usb_avsf2 117 v2 usb_mode 217 ad6 ide_dd[10] 317 aa23 mcas 417 e9 vdde 18 v1 usb_cryck48 118 w2 vin1[5] 218 ad7 ide_dd[6] 318 y23 mdq[3] 418 e8 vdde 19 w1 vin1[6] 119 y2 vin1[2] 219 ad8 ide_dd[2] 319 w23 mdq[4] 419 e7 vss 20 y1 vss 120 aa2 vdde 220 ad9 ide_da[1] 320 v23 mdm[0] 420 e6 vss 21 aa1 cclk1 121 ab2 i2s_sdo2 221 ad10 ide_xdior 321 u23 mdq[11] 421 k10 vddi 22 ab1 vinfid1 122 ac2 pwm_o1 222 ad11 mpx_mode_1[1] 322 t23 mdq[12] 422 l10 vddi 23 ac1 i2s_sck2 123 ad2 pwm_o0 223 ad12 pllbypass 323 r23 mdq[14] 423 m10 vdd e 24 ad1 i2s_eclk2 124 ae2 vss 224 ad13 ad_vin0 324 p23 ocd 424 n10 vdde 25 ae1 vss 125 ae3 ide_xdasp 225 ad14 ad_vin1 325 n23 odt 425 p10 vddi 26 af1 vss 126 ae4 ide_xddmack 226 ad15 vdde 326 m23 mdq[19] 426 r10 vddi 27 af2 vss 127 ae5 ide_dd[13] 227 ad16 uart_sout2 327 l23 mdq[20] 427 t10 vdd e 28 af3 ide_xiocs16 128 ae6 ide_dd[9] 228 ad17 sd_cmd 328 k23 mdm[2] 428 u10 v dde 29 af4 ide_xdreset 129 ae7 ide_dd[5] 229 ad18 sd_dat[2] 329 j23 mdq[27] 429 u11 vddi 30 af5 ide_dd[12] 130 ae8 ide_dd[1] 230 ad19 usb_prtpwr 330 h23 mdq[25] 430 u12 vddi 31 af6 ide_dd[8] 131 ae9 ide_da[0] 231 ad20 i2c_sda0 331 g23 mdq[30] 431 u13 vdde 32 af7 ide_dd[4] 132 ae10 ide_xdcs[0] 232 ad21 int_a[1] 332 f23 mem_ed[2] 4 32 u14 vdde 33 af8 ide_dd[0] 133 ae11 mpx_mode_5[0] 233 ad22 testmode[2] 333 e23 mem_e d[6] 433 u15 vddi 34 af9 ide_csel 134 ae12 bigend 234 ad23 ma[9] 334 d23 mem_ed[10] 434 u16 vdd i 35 af10 ide_xdcs[1] 135 ae13 ad_vrh0 235 ad24 ma[6] 335 d22 mem_ea[5] 435 u1 7 ddrvde 36 af11 mpx_mode_5[1] 136 ae14 ad_vrh1 236 ac24 ma[2] 336 d21 mem_ea[9] 436 t17 ddrvde 37 af12 testmode[1] 137 ae15 uart_xrts0 237 ab24 mwe 337 d20 mem_ea[13] 437 r17 vddi 38 af13 ad_avd 138 ae16 uart_xcts0 238 aa24 mras 338 d19 mem_ea[17] 438 p17 v ddi 39 af14 ad_avs 139 ae17 uart_sout1 239 y24 mdq[5] 339 d18 mem_ea[21] 439 n17 ddrvde 40 af15 uart_sout0 140 ae18 sd_dat[1] 240 w24 mdq[1] 340 d17 mem_ea[24] 440 m17 ddrvde 41 af16 uart_sin0 141 ae19 sd_xmcd 241 v24 mdq[7] 341 d16 mem_xcs[0] 441 l17 vddi 42 af17 uart_sin1 142 ae20 i2c_scl0 242 u24 mdq[10] 342 d15 mem_rdy 442 k17 v ddi 43 af18 sd_dat[0] 143 ae21 int_a[3] 243 t24 mdq[9] 343 d14 cripm1 443 k16 vdd e 44 af19 sd_wp 144 ae22 mcke_start 244 r24 mdm[1] 344 d13 tdi 444 k15 vdde 45 af20 i2c_scl1 145 ae23 ma[13] 245 p24 vss 345 d12 plltdtrst 445 k14 vddi 46 af21 i2c_sda1 146 ae24 ma[4] 246 n24 vss 346 d11 tracedata[2] 446 k13 vddi 47 af22 int_a[0] 147 ae25 ma[11] 247 m24 mdq[18] 347 d10 rtck 447 k12 vdde 48 af23 ma[8] 148 ad25 ma[5] 248 l24 mdq[17] 348 d9 doutb0[3] 448 k11 vdde 49 af24 ma[12] 149 ac25 ma[10] 249 k24 mdq[23] 349 d8 doutb0[7] 449 l11 vss 50 af25 vss 150 ab25 mba[0] 250 j24 mdq[26] 350 d7 doutg0[5] 450 m11 vss 51 af26 vss 151 aa25 mcke 251 h24 mdq[28] 351 d6 doutr0[3] 451 n11 vss 52 ae26 ma[7] 152 y25 mdq[2] 252 g24 mdm[3] 352 d5 doutr0[6] 452 p11 vss 53 ad26 ma[3] 153 w25 mdq[0] 253 f24 mem_ed[1] 353 e5 vdde 453 r11 vss 54 ac26 ma[1] 154 v25 vref0 254 e24 mem_ed[5] 354 f5 vdde 454 t11 vss 55 ab26 mba[1] 155 u25 mdq[13] 255 d24 mem_ed[9] 355 g5 vddi 455 t12 vss 56 aa26 vss 156 t25 mdq[8] 256 c24 mem_ed[13] 356 h5 vddi 456 t13 vss 57 y26 mdqsn[0] 157 r25 mdq[15] 257 c23 mem_ea[2] 357 j5 vss 457 t14 vss 58 w26 mdqsp[0] 158 p25 ddrvde 258 c22 mem_ea[6] 358 k5 vss 458 t15 vss 59 v26 vss 159 n25 ddrvde 259 c21 mem_ea[10] 359 l5 vdde 459 t16 vss 60 u26 mdqsn[1] 160 m25 mdq[21] 260 c20 mem_ea[14] 360 m5 vdde 460 r16 vss 61 t26 mdqsp[1] 161 l25 mdq[16] 261 c19 mem_ea[18] 361 n5 vddi 461 p16 vss 62 r26 vss 162 k25 vref1 262 c18 mem_ea[22] 362 p5 usb_avdb 462 n16 vss 63 p26 mckn 163 j25 mdq[29] 263 c17 mem_xwr[0] 363 r5 usb_ext12k 463 m16 vss 64 n26 mckp 164 h25 mdq[24] 264 c16 mem_xcs[2] 364 t5 usb_avsf2 464 l16 vss 65 m26 vss 165 g25 mdq[31] 265 c15 cripm0 365 u5 vddi 465 l15 vss 66 l26 mdqsn[2] 166 f25 mem_ed[0] 266 c14 cripm2 366 v5 vddi 466 l14 vss 67 k26 mdqsp[2] 167 e25 mem_ed[4] 267 c13 tck 367 w5 vdde 467 l13 vss 68 j26 vss 168 d25 mem_ed[8] 268 c12 jtagsel 368 y5 vdde 468 l12 vss 69 h26 mdqsn[3] 169 c25 mem_ed[12] 269 c11 tracedata[1] 369 aa5 vss 469 m12 v ss 70 g26 mdqsp[3] 170 b25 mem_ed[14] 270 c10 traceclk 370 ab5 vss 470 n12 vss 71 f26 vss 171 b24 mem_ed[15] 271 c9 doutb0[2] 371 ab6 vdde 471 p12 vss 72 e26 mem_ed[3] 172 b23 mem_ea[3] 272 c8 doutb0[6] 372 ab7 vdde 472 r12 vss 73 d26 mem_ed[7] 173 b22 mem_ea[7] 273 c7 doutg0[4] 373 ab8 vddi 473 r13 vss 74 c26 mem_ed[11] 174 b21 mem_ea[11] 274 c6 doutr0[2] 374 ab9 vddi 474 r14 vs s 75 b26 vss 175 b20 mem_ea[15] 275 c5 doutr0[5] 375 ab10 vss 475 r15 vss 76 a26 vss 176 b19 mem_ea[19] 276 c4 doutr0[7] 376 ab11 vss 476 p15 vss 77 a25 vss 177 b18 mem_ea[23] 277 d4 doutb1[3] 377 ab12 vdde 477 n15 vss 78 a24 mem_ea[1] 178 b17 mem_xwr[1] 278 e4 doutb1[7] 378 ab13 ad_vrl0 478 m1 5vss 79 a23 mem_ea[4] 179 b16 mem_xcs[4] 279 f4 doutg1[5] 379 ab14 ad_vrl1 479 m1 4vss 80 a22 mem_ea[8] 180 b15 vdde 280 g4 doutr1[3] 380 ab15 vss 480 m13 vss 81 a21 mem_ea[12] 181 b14 cripm3 281 h4 doutr1[6] 381 ab16 vss 481 n13 vss 82 a20 mem_ea[16] 182 b13 vinithi 282 j4 hsync1 382 ab17 vss 482 p13 vss 83 a19 mem_ea[20] 183 b12 tms 283 k4 de1 383 ab18 vdde 483 p14 vss 84 a18 vss 184 b11 tracedata[0] 284 l4 vin0[4] 384 ab19 vdde 484 n14 vss 85 a17 mem_xrd 185 b10 tracectl 285 m4 vin0[0] 385 ab20 vddi 86 a16 clk 186 b9 xtrst 286 n4 vddi 386 ab21 vddi 87 a15 vss 187 b8 doutb0[5] 287 p4 usb_avsb 387 ab22 ddrvde 88 a14 tdo 188 b7 doutg0[3] 288 r4 usb_avsf2 388 aa22 ddrvde 89 a13 pllvdd 189 b6 doutg0[7] 289 t4 usb_avsf2 389 y22 vss 90 a12 pllvss 190 b5 doutr0[4] 290 u4 vss 390 w22 vss 91 a11 xrst 191 b4 vdde 291 v4 vss 391 v22 mdq[6] 92 a10 tracedata[3] 192 b3 hsync0 292 w4 vin1[3] 392 u22 ddrvde 93 a9 xsrst 193 c3 vsync0 293 y4 vin1[0] 393 t22 ddrvde 94 a8 doutb0[4] 194 d3 doutb1[4] 294 aa4 vinhsync1 394 r22 vss 95 a7 doutg0[2] 195 e3 doutg1[2] 295 ab4 i2s_ws2 395 p22 vddi 96 a6 doutg0[6] 196 f3 doutg1[6] 296 ac4 ide_dintrq 396 n22 vddi 97 a5 dclkin0 197 g3 doutr1[4] 297 ac5 ide_dd[15] 397 m22 vss 98 a4 vss 198 h3 doutr1[7] 298 ac6 ide_dd[11] 398 l22 mdq[22] 99 a3 dclko0 199 j3 vsync1 299 ac7 ide_dd[7] 399 k22 ddrvde 100 a2 vss 200 k3 vin0[7] 300 ac8 ide_dd[3] 400 j22 ddrvde 10 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 7. pin function external pin function of MB86R01 is described below. 7.1. pin multiplex this lsi adopts pin multiplex function, and a part of external pin function is multiplexed. the external pin function is categorized into following five groups. each group is able to set the external pin function individually; therefore, the function can be flexibly set depending on the peripheral i/o resource to be used. 1. pin multiplex group #1 (setting pin: mpx_mode_1[1:0]) ? mode 0: pin related to display1 ? mode 1: pin related to external bus interface ? mode 2: pin related to i2s0, gpio, and display0 data width extension 2. pin multiplex group #2 (setting register: cmux_md.mpx_mode_2[2:0]) ? mode 0: pin related to cap1, cap0 synchronizing signal, pwm, and i2s2 ? mode 1: pin related to cap1 (nrgb666) ? mode 2: pin related to gpio, can, i2s1, medialb, and i2s2 ? mode 3: pin related to gpio, can, i2s1, medialb, and spi ? mode 4: pin related to gpio, can, i2s1, medialb, and i2s2 (input) 3. pin multiplex group #3 (setting pin: usb_mode) ? mode 0: pin related to usb 2.0 host ? mode 1: pin related to usb 2.0 function 4. pin multiplex group #4 (setting register: cmux_md.mpx_mode_4[1:0]) ? mode 0: pin related to ide ? mode 1: pin related to i2s1, can, gpio, and pwm 5. pin multiplex group #5 (setting pin: mpx_mode_5[1:0]) ? mode 0: pin related to etm ? mode 1: pin related to uart3, uart4, and uart5 ? mode 2: pin related to uart3, uart4, and pwm note: mode should be changed when each pin is not in operation. pwm, i2s1, and can pins may be duplicated and allocated to external pin depending on group combination; in this case, use either of them. for unused pin, follow the procedure in 1.6.27, unused pin with pin multiplex function in the duplex case. 11 fujitsu microelectronics proprietary and confidential MB86R01 data sheet pin multiplex group #1 (setting pin: mpx_mode_1 [1:0]) mode 0 mode 1 mode 2 pin no. jedec pin related to display1 pin related to external bus interface pin related to i2s0 pin related to gpio pin related to display0 pin related to external bus interface 198 h3 doutr1[7] mem_ed[31] i2s_eclk0 - - - 281 h4 doutr1[6] mem_ed[30] i2s_sck0 - - - 106 g2 doutr1[5] mem_ed[29] i2s_ws0 - - - 197 g3 doutr1[4] mem_ed[28] i2s_sdi0 - - - 280 g4 doutr1[3] mem_ed[27] i2s_sdo0 - - - 6 f1 doutr1[2] mem_ed[26] - gpio_pd[12] - - 105 f2 doutg1[7] mem_ed[25] - gpio_pd[11] - - 196 f3 doutg1[6] mem_ed[24] - gpio_pd[10] - - 279 f4 doutg1[5] mem_ed[23] - gpio_pd[9] - - 5 e1 doutg1[4] mem_ed[22] - gpio_pd[8] - - 104 e2 doutg1[3] mem_ed[21] - gpio_pd[7] - - 195 e3 doutg1[2] mem_ed[20] - gpio_pd[6] - - 278 e4 doutb1[7] mem_ed[19] - - doutr0[1] - 4 d1 doutb1[6] mem_ed[18] - - doutr0[0] - 103 d2 doutb1[5] mem_ed[17] - - doutg0[1] - 194 d3 doutb1[4] mem_ed[16] - - doutg0[0] - 277 d4 doutb1[3] mem_xwr[3] - - doutb0[1] - 3 c1 doutb1[2] mem_xwr[2] - - doutb0[0] - 283 k4 de1 xdack[7] - - - xdack[7] 282 j4 hsync1 dreq[6] - - - dreq[6] 199 j3 vsync1 xdack[6] - - - xdack[6] 108 j2 gv1 dreq[7] - - - dreq[7] pin multiplex group #1 mode setting this mode is set with external pin, mpx_mode_1[1:0]. mpx_mode_1[1] pin mpx_mode_1[0] pin pin multiplex group #1 mode "l" "l" mode 0 "l" "h" mode 1 "h" "l" mode 2 "h" "h" mode 0 12 fujitsu microelectronics proprietary and confidential MB86R01 data sheet pin multiplex group #2 (setting register: pin mpx select.mpx_mode_2 [2:0]) mode0 mode1 mode2 mode3 mode4 pin no. jedec pin related to cap0/1 pin related to pwm pin related to i2s2 pin related to cap1 (nrgb666) pin related to gpio pin related to can pin related to i2s1/2 pin related to medialb pin related to gpio pin related to can pin related to i2s1 pin related to medialb pin related to spi pin related to gpio pin related to can pin related to i2s1/2 pin related to medialb 208 v3 vin1[7] - - ri1[7] gpio_pd[5] - - - gpio_pd[5] - - - - gpio_pd[5] - - - 19 w1 vin1[6] - - ri1[6] gpio_pd[4] - - - gpio_pd[4] - - - - gpio_pd[4] - - - 118 w2 vin1[5] - - ri1[5] - can_tx0 - - - can_tx0 - - - - can_tx0 - - 209 w3 vin1[4] - - ri1[4] - can_rx0 - - - can_rx0 - - - - can_rx0 - - 292 w4 vin1[3] - - ri1[3] - can_tx1 - - - can_tx1 - - - - can_tx1 - - 119 y2 vin1[2] - - ri1[2] - can_rx1 - - - can_rx1 - - - - can_rx1 - - 210 y3 vin1[1] - - gi1[7] - - i2s_sck1 - - - i2s_sck1 - - - - i2s_sck1 - 293 y4 vin1[0] - - gi1[6] - - i2s_ws1 - - - i2s_ws1 - - - - i2s_ws1 - 211 aa3 vinvsync1 - - vinvsync1 - - i2s_eclk1 - - - i2s_eclk1 - - - - i2s_eclk1 - 294 aa4 vinhsync1 - - vinhsync1 - - i2s_sdi1 - - - i2s_sdi1 - - - - i2s_sdi1 - 22 ab1 vinfid1 - - vinfid1 - - i2s_sdo1 - - - i2s_sdo1 - - - - i2s_sdo1 - 202 m3 vinvsync0 - - gi1[5] - - - mlb_data - - - mlb_data - - - - mlb_data 203 n3 vinhsync0 - - gi1[4] - - - mlb_sig - - - mlb_sig - - - - mlb_sig 112 n2 vinfid0 - - gi1[3] - - - mlb_clk - - - mlb_clk - - - - mlb_clk 123 ad2 - pwm_o0 - gi1[2] gpio_pd[3] - - - gpio_pd[3] - - - - gpio_pd[3] - - - 122 ac2 - pwm_o1 - bi1[7] gpio_pd[2] - - - gpio_pd[2] - - - - gpio_pd[2] - - - 121 ab2 - - i2s_sdo2 bi1[6] - - i2s_sdo2 - - - - - spi_do gpio_pd[1] - - - 24 ad1 - - i2s_eclk2 bi1[5] - - i2s_eclk2 - - - - - reserved (input/outpu t) gpio_pd[0] - - - 23 ac1 - - i2s_sck2 bi1[4] - - i2s_sck2 - - - - - spi_sck - - i2s_sck2 - 295 ab4 - - i2s_ws2 bi1[3] - - i2s_ws2 - - - - - spi_ss - - i2s_ws2 - 212 ab3 - - i2s_sdi2 bi1[2] - - i2s_sdi2 - - - - - spi_di - - i2s_sdi2 - pin multiplex group #2 mode setting this mode is set with mpx_mode_2 bit (bit 2- 0) in the multiplex mode setting register (cmux_md.) mpx_mode_2 (bit 2-0) of the cmux_md register pin multiplex group #2 mode 000 mode 0 001 mode 1 010 mode 2 011 mode 3 100 mode 4 101 ? 0110 reserved 111 (initial value) 13 fujitsu microelectronics proprietary and confidential MB86R01 data sheet pin multiplex group #3 (setting pin: usb_mode) mode 0 mode 1 pin no. jedec pin related to usb 2.0 host pin related to usb 2.0 function 114 r2 usb_fsdp usb_fsdp 115 t2 usb_fsdm usb_fsdm 15 r1 usb_hsdp usb_hsdp 16 t1 usb_hsdm usb_hsdm 18 v1 usb_cryck48 usb_cryck48 230 ad19 usb_prtpwr usb_prtpwr pin multiplex group #3 mode setting this mode is set with external pin, usb_mode. usb_mode pin pin multiplex group #3 mode "l" mode 0 "h" mode 1 14 fujitsu microelectronics proprietary and confidential MB86R01 data sheet pin multiplex group #4 (setting register: pin_mpx_select.mpx_mode_4 [1:0]) mode 0 mode 1 pin no. jedec pin related to ide pin related to i2s1 pin related to can pin related to gpio pin related to pwm unused pin (input/output) 29 af4 ide_xdreset - - - - reserved (output) 28 af3 ide_xiocs16 i2s_sdi1 - - - - 125 ae3 ide_xdasp i2s_ws1 - - - - 215 ad4 ide_ddmarq i2s_eclk1 - - - - 296 ac4 ide_dintrq i2s_sdo1 - - - - 214 ad3 ide_xcblid i2s_sck1 - - - - 297 ac5 ide_dd[15] - can_tx0 - - - 216 ad5 ide_dd[14] - can_rx0 - - - 127 ae5 ide_dd[13] - can_tx1 - - - 30 af5 ide_dd[12] - can_rx1 - - - 298 ac6 ide_dd[11] - - gpio_pd[23] - - 217 ad6 ide_dd[10] - - gpio_pd[22] - - 128 ae6 ide_dd[9] - - gpio_pd[21] - - 31 af6 ide_dd[8] - - gpio_pd[20] - - 299 ac7 ide_dd[7] - - gpio_pd[19] - - 218 ad7 ide_dd[6] - - gpio_pd[18] - - 129 ae7 ide_dd[5] - - gpio_pd[17] - - 32 af7 ide_dd[4] - - gpio_pd[16] - - 300 ac8 ide_dd[3] - - gpio_pd[15] - - 219 ad8 ide_dd[2] - - gpio_pd[14] - - 130 ae8 ide_dd[1] - - gpio_pd[13] - - 33 af8 ide_dd[0] - - - - reserved (input/output) 213 ac3 ide_diordy - - - - reserved (input) 301 ac9 ide_da[2] - - - - reserved (output) 220 ad9 ide_da[1] - - - pwm_o1 - 131 ae9 ide_da[0] - - - pwm_o0 - 35 af10 ide_xdcs[1] - - - - reserved (output) 132 ae10 ide_xdcs[0] - - - - reserved (output) 221 ad10 ide_xdior - - - - reserved (output) 302 ac10 ide_xdiow - - - - reserved (output) 34 af9 ide_csel - - - - reserved (output) 126 ae4 ide_xddmack - - - - reserved (output) pin multiplex group #4 mode setting this mode is set with mpx_mode_4 bit (bit 5- 4) in the multiplex mode setting register (cmux_md.) mpx_mode_4 (bit 5-4) of the cmux_md register pin multiplex group #4 mode 00 mode 0 01 mode 1 10 reserved 11 (initial value) 15 fujitsu microelectronics proprietary and confidential MB86R01 data sheet pin multiplex group #5 (setting pin: mpx_mode_5 [1:0]) mode 0 mode 1 mode 2 pin no. jedec pin related to etm pin related to uart3/4/5 pin related to uart3/4 pin related to pwm 270 c10 traceclk uart_sin3 uart_sin3 - 185 b10 tracectl uart_sout3 uart_sout3 - 92 a10 tracedata[3] uart_sin4 uart_sin4 - 346 d11 tracedata[2] uart_sout4 uart_sout4 - 269 c11 tracedata[1] uart_sin5 - pwm_o1 184 b11 tracedata[0] uart_sout5 - pwm_o0 pin multiplex group #5 mode setting this mode is set with external pin, mpx_mode_5[1:0]. mpx_mode_5[1] pin mpx_mode_5[0] pin pin multiplex group #5 mode "l" "l" mode 0 "l" "h" mode 1 "h" "l" mode 2 "h" "h" mode 0 16 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 7.2. pin function format pin function list is shown in the following format. pin name i/o polarity analog /digital type status of pin after reset description meaning of item and sign pin name name of external pin. i/o input/output signal's distinction based on this lsi. ? i: pin that can be used as input ? o: pin that can be used as output ? io: pin that can be used as input and output (interactive pin) polarity active polarity of external pin's input/output signals ? p: "h" active pin (positive logic) ? n: "l" active pin (negative logic) ? pn: "h" and "l" active pins analog/digital signal type of external pin ? a: analog signal ? d: digital signal type input/output circuit type of external pin. ? clk: ? pod: pseudo open drain ? pu: pull up ? pd: pull down ? st: schmitt type ? tri: tri-state pin status after reset pin status after external pin reset ? h: "h" level ? l: "l" level ? hiz: high impedance ? x: "h" level or "l" level ? a: clock output description outline of external pin function 17 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 7.2.1. external bus interface related pin pin name i/o polarity analog /digital type status of pin after reset description mem_xcs[4] o n d - h chip select 4 mem_xcs[2] o n d - h chip select 2 mem_xcs[0] o n d - h chip select 0 mem_xrd o n d - h read strobe mem_xwr[3:2] o n d - h write strobe mem_xwr[3] -> mem_ed[31:24], mem_xwr[2] -> mem_ed[23:16] (optional pin) mem_xwr[1:0] o n d - h write strobe mem_xwr[1] -> mem_ed[15:8], mem_xwr[0] -> mem_ed[7:0] mem_rdy i p d - - ready input for slow device mem_ea[24:1] o - d - l address bus mem_ed[31:16] io - d - hiz bi-directional data bus (optional pin) mem_ed[15:0] io - d - hiz bi-directional data bus dreq[7:6] i - d - - external dma request xdack[7:6] o p d - l external dma acknowledge 7.2.2. ide66 related pin pin name i/o polarity analog /digital type status of pin after reset description ide_xdreset o n d - h ide reset ide_dd[15:0] io - d pd l ide device data ide_xdcs[1:0] o n d - h ide chip select ide_da[2:0] o p d - l ide device address ide_xdior o n d - h ide device i/o read ide_xdiow o n d - h ide device i/o write ide_diordy i p d - - ide i/o channel ready ide_ddmarq i p d - - ide device dma request ide_xddmack o n d - h ide device dma acknowledge ide_csel o p d - l ide cable select ide_xiocs16 i n d - - ide 16 bit i/o ide_xdasp i n d pd - ide device active ide_dintrq i p d pd - ide interrupt ide_xcblid i n d pd - ide cable id 18 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 7.2.3. sd memory controller related pin pin name i/o polarity analog /digital type status of pin after reset description sd_clk o n d - l media clock sd_cmd io - d - hiz media command sd_dat[3:0] io - d - hiz media data sd_wp i p d - - media write protection sd_xmcd i n d - - media card detection 7.2.4. usb 2.0 host/function related pin pin name i/o polarity analog /digital type status of pin after reset description usb_fsdp io - a - - d+ for fs usb_fsdm io - a - - d- for fs usb_hsdp io - a - - d+ for hs usb_hsdm io - a - - d- for hs usb_cryck48 i - d clk - clock used for usb communication usb_prtpwr o - d - l usb port power control usb_ext12k o - a - - external resistance pin this should be connected to usb_avdb through 12k resistance. usb_avsp i - a - - pll ground usb_avsb i - a - - reference voltage ground usb_avdp i - a - - pll power supply usb_avdb i - a - - reference voltage power supply usb_avsf1 i - a - - driver/receiver ground 1 usb_avdf1 i - a - - driver/receiver power supply 1 usb_avsf2 i - a - - driver/receiver ground 2 usb_avdf2 i - a - - driver/receiver power supply 2 7.2.5. external interrupt controller related pin pin name i/o polarity analog /digital type status of pin after reset description int_a[3:0] i pn d - - asynchronous external interrupt requests 19 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 7.2.6. uart related pin pin name i/o polarity analog /digital type status of pin after reset explanation uart_sin0 i p d - - input data signal uart_sout0 o p d - h output data signal uart_xcts0 i n d - - clear to send uart_xrts0 o n d - h request to send uart_sin1 i p d - - input data signal uart_sout1 o p d - h output data signal uart_sin2 i p d - - input data signal uart_sout2 o p d - h output data signal uart_sin3 i p d - - input data signal (optional) uart_sout3 o p d - h output data signal (optional) uart_sin4 i p d - - input data signal (optional) uart_sout4 o p d - h output data signal (optional) uart_sin5 i p d - - input data signal (optional) uart_sout5 o p d - h output data signal (optional) 7.2.7. can related pin pin name i/o polarity analog /digital type status of pin after reset explanation can_tx0 o - d pd h transmission (optional) can_rx0 i - d pd - reception (optional) can_tx1 o - d pd h transmission (optional) can_rx1 i - d pd - reception (optional) 7.2.8. i2s related pin pin name i/o polarity analog /digital type status of pin after reset explanation i2s_eclk0 i - d - - external clock (optional) i2s_sck0 io - d - hiz clock (optional) i2s_ws0 io pn d - hiz sync (optional) i2s_sdi0 i p d - - input data signal (optional) i2s_sdo0 o p d - hiz output data signal (optional) i2s_eclk1 i - d - - external clock (optional) i2s_sck1 io - d pd l clock (optional) i2s_ws1 io pn d pd l sync(optional) i2s_sdi1 i p d - - input data signal (optional) i2s_sdo1 o p d pd l output data signal (optional) i2s_eclk2 i - d pd - external clock (optional) i2s_sck2 io - d pd l clock (optional) i2s_ws2 io pn d pd l sync (optional) i2s_sdi2 i p d - - input data signal (optional) i2s_sdo2 o p d pd l output data signal (optional) 20 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 7.2.9. i 2 c related pin pin name i/o polarity analog /digital type status of pin after reset explanation i2c_scl0 io - d pod hiz i2c clock i2c_sda0 io - d pod hiz i2c data i2c_scl1 io - d pod hiz i2c clock i2c_sda1 io - d pod hiz i2c data 7.2.10. spi related pin pin name i/o polarity analog /digital type status of pin after reset explanation spi_do o p d pd l serial data output (optional) spi_di i p d - - serial data input (optional) spi_sck o - d pd l serial clock (optional) spi_ss o pn d pd l slave select (optional) 7.2.11. pwm related pin pin name i/o polarity analog /digital type status of pin after reset explanation pwm_o0 o - d pd (*1) l pwm out 0 (optional) pwm_o1 o - d pd (*1) l pwm out 1 (optional) *1: only pwm pin of the pin multiplex group #2 is with pull-down resistance. 7.2.12. a/d converter related pin pin name i/o polarity analog /digital type status of pin after reset explanation ad_vin0 i - a - - a/d analog input ad_vrh0 i - a - - reference voltage "h" input ad_vrl0 i - a - - refere nce voltage "l" input ad_avd i - a - - analog power supply ad_vr0 o - a - - reference output ad_vin1 i - a - - a/d analog input ad_vrh1 i - a - - reference voltage "h" input ad_vrl1 i - a - - refere nce voltage "l" input ad_avs i - a - - analog ground ad_vr1 o - a - - reference output 21 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 7.2.13. ddr2 related pin pin name i/o polarity analog /digital type status of pin after reset explanation ma[13:0] o p d - h address mba[1:0] o p d - h bank address mdq[31:0] io p d - h data (*5) mdm[3:0] o p d - hiz data mask (*6) mdqsp[3:0] io p d - hi z data strobe (*5) mdqsn[3:0] io n d - hi z data strobe (*5) mckp o p d clk l clock output mckn o n d clk h clock output mcke o p d - l clock enable mcs o n d - l chip select mras o n d - h row address strobe mcas o n d - h column address strobe mwe o n d - h write enable ddrvde i - a - - sstl_18 1.8v power supply vref1 i - a - - reference voltage input (ddrvde/2) vref0 i - a - - reference voltage input (ddrvde/2) ocd o - a - - off chip driver reference voltage input (*1) odt o - a - - on-die terminati on reference voltage input (*2) odtcont o p d - l on-die termination control (*3) mcke_start i p d - - set a state of mcke in reset 0: low (*4) 1: high (reserved) ddrtype i p d - - pull-up pin to vdde via high resistance *1: pull up the pin to ddrvde (1.8v power supply), via 200 resistance *2: pcb impedance z = 100 or 50 : pull up pin to ddrvde (1.8v power supply), via a 180 resistance. pcb impedance z = 150 or 75 : pull up pin to ddrvde (1.8v power supply), via a 240 resistance. *3: it connects it with the odt pin of ddr2sdram *4: pull down pin to v ss, via high resistance *5: this is process of unused pin at 16 bit mode . pull down the pin to vss via high resistance. unused pins at 16 bi t mode are as follows: "mdq[31:16], mdqsp[3:2], mdqsn[3:2]" *6: this is process of mdm[3:2] at 16 bit mode. be sure to open this pin. 22 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 7.2.14. display related pin pin name i/o polarity analog /digital type status of pin after reset explanation hsync0 io - d - hiz video output interface horizontal sync output horizontal sync input in external sync mode vsync0 io - d - hiz video output interface vertical sync output vertical sync input in external sync mode gv0 o - d - l video output interface graphics/video switch dclkin0 i - d clk - video output interface dot clock input dclko0 o - d clk x video outpu t interface dot clock output de0 o - d - x de/csync doutr0[7:2] o - d - x digita l rgb output0 datar[7:2] doutr0[1:0] o - d - x digital rgb output0 datar[1:0] (optional) doutg0[7:2] o - d - x digita l rgb output0 datag[7:2] doutg0[1:0] o - d - x digital rgb output0 datag[1:0] (optional) doutb0[7:2] o - d - x digita l rgb output0 datab[7:2] doutb0[1:0] o - d - x digital rgb output0 datab[1:0] (optional) hsync1 io - d - hiz video output interface horizontal sync output horizontal sync input in external sync mode vsync1 io - d - hiz video output interface vertical sync output vertical sync input in external sync mode gv1 o - d - l video output interface graphics/video switch dclkin1 i - d clk - video output interface dot clock input dclko1 o - d clk x video outpu t interface dot clock output de1 o - d - x de/csync doutr1[7:2] o - d - x digita l rgb output1 datar[7:2] doutg1[7:2] o - d - x digita l rgb output1 datag[7:2] doutb1[7:2] o - d - x digita l rgb output1 datab[7:2] note: when r:g:b = 5:5:5, lower 1 bit is set with the data contents of the upper 5 bits. [upper 5 bits] [lower 1 bit] doutr0[7:3]=00000 -> doutr0[2]=0 (low) doutr0[7:3]=00001-11111 -> doutr0[2]=1 (high) doutr1[7:3]=00000 -> doutr1[2]=0 (low) doutr1[7:3]=00001-11111 -> doutr1[2]=1 (high) doutg0[7:2], doutg1[7:2], doutb0[7:2], and doutb1[7:2] have also the same spec. 23 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 7.2.15. video capture related pin pin name i/o polarity analog /digital type status of pin after reset description vin0[7:0] i - d - - video capture data[7:0] vinvsync0 i - d pd - video capture vertical sync input vinhsync0 i - d pd - video capture horizontal sync input vinfid0 i - d - - video input fi eld identification signal 0 in odd field cclk0 i - d clk - video capture input clock vin1[7:0] i - d pd - video capture data[7:0] vinvsync1 i - d - - video capture vertical sync input vinhsync1 i - d - - video capture horizontal sync input vinfid1 i - d pd - video input fi eld identification signal 0 in odd field cclk1 i - d clk - video capture input clock ri1[7:2] i - d pd - nrgb666 capture datar[7:2] (optional) gi1[7:2] i - d pd (*1) - nrgb666 capture datag[7:2] (optional) bi1[7:2] i - d pd (*2) - nrgb666 capture datab[7:2] (optional) *1: gi1[3] is not applicable. *2: bi1[2] is not applicable. 7.2.16. system related pin pin name i/o polarity analog /digital type status of pin after reset description clk i - d clk - input clock xrst i n d st - system reset cripm[3:0] i - d - - pllmode setting vinithi i - d - - boot high address pllbypass i - d - - pll bypass mode setting bigend i - d - - lsi endian setting low: little endian high: big endian pllvss i - a - - pll ground plltdtrst i - d - - test pin pull up the pin to vdde, via high resistance pllvdd i - a - - pll power supply 7.2.17. jtag related pin pin name i/o polarity analog /digital type status of pin after reset description tck i - d st, pu - test clock xtrst i n d st, pu - test reset tms i n d pu - test mode tdi i - d pu - test data input tdo o - d tri hiz test data output 24 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 7.2.18. ice related pin pin name i/o polarity analog /digital type status of pin after reset description rtck o - d - h return test clock xsrst io n d st, pu h system reset 7.2.19. multiplex setting related pin pin name i/o polarity analog /digital type status of pin after reset description jtagsel i - d - - jtag selection 1: dft, 0: normal pull it down to vss, via high resistance mpx_mode_5[1:0] i - d - - external pin multiplex mode 5 mpx_mode_1[1:0] i - d - - external pin multiplex mode 1 usb_mode i - d - - usb selection 0: host, 1: function testmode[2:0] i - d - - test mode selection pin pull it down to vss, via high resistance vpd i - d - - test mode selection pin pull it down to vss, via high resistance 7.2.20. etm related pin pin name i/o polarity analog /digital type status of pin after reset description traceclk o - d - l exported clock for tracedata[3:0] and tracectl they are valid on bath edges of traceclk for max. integrity. tracectl o - d - h trace control signal used by the trace tool such as realview supplied by arm limited. tracedata[3:0] o - d - lhhh trace da ta used by the trace tool such as realview supplied by arm limited. 7.2.21. power supply related pin pin name i/o polarity analog /digital type status of pin after reset description vss i - d - - ground vdde i - d - - external pin power supply vddi i - d - - internal power supply 25 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 7.2.22. medialb related pin pin name i/o polarity analog /digital type status of pin after reset description mlb_data io p d pd hiz data (optional) (*1) mlb_sig io p d pd hiz control (optional) (*1) mlb_clk i - d clk - clock (optional) (*1) *1: medialb pin of this lsi uses 3.3[v] i/o; therefore, wh en connecting bus's voltage is not 3.3[v], level conversion at external side is needed. 7.2.23. gpio related pin pin name i/o polarity analog /digital type status of pin after reset description gpio_pd[23:0] io - d pd (*1) hiz general purpose i/o port (optional) *1: gpio_pd[12:6] is not applicable. 26 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 7.2.24. unused pin proceed following proces ses for unused pin. pin no. jedec pin name process 3 c1 doutb1[2], mem_xwr[2], doutb0[0] 4 d1 doutb1[6], mem_ed[18], doutr0[0] pull up to vdde or pull down to vss through high resistance. 5 e1 doutg1[4], mem_ed[22], gpio_pd[8] 6 f1 doutr1[2], mem_ed[26], gpio_pd[12] 7 g1 dclkin1 9 j1 dclko1 keep the pin open. 10 k1 vin0[5] 11 l1 vin0[1] pull up to vdde or pull down to vss through high resistance. 12 m1 cclk0 14 p1 usb_avsp connect to vss. 15 r1 usb_hsdp 16 t1 usb_hsdm pull down to vss through 10k ? resistance. 17 u1 usb_avsf2 connect to vss. 18 v1 usb_cryck48 pull up to vdde or pull down to vss through high resistance. 19 w1 vin1[6], ri1[6], gpio_pd[4] keep the pin open. 21 aa1 cclk1 pull up to vdde or pull down to vss through high resistance. 22 ab1 vinfid1, i2s_sdo1 keep the pin open. 23 ac1 i2s_sck2, bi1[4], spi_sck 24 ad1 i2s_eclk2, bi1[5], reserved (input/output), gpio_pd[0] 28 af3 ide_xiocs16, i2s_sdi1 pull up to vdde or pull down to vss through high resistance. 29 af4 ide_xdreset, reserved (output) keep the pin open. 30 af5 ide_dd[12], can_rx1 31 af6 ide_dd[8], gpio_pd[20] 32 af7 ide_dd[4], gpio_pd[16] 33 af8 ide_dd[0], reserved (input/output) 34 af9 ide_csel, reserved (output) 35 af10 ide_xdcs[1], reserved (output) 36 af11 mpx_mode_5[1] pull up to vdde or pull down to vss through high resistance. 38 af13 ad_avd connect to vss. 39 af14 ad_avs 40 af15 uart_sout0 keep the pin open. 41 af16 uart_sin0 pull up to vdde or pull down to vss through high resistance. 42 af17 uart_sin1 43 af18 sd_dat[0] 44 af19 sd_wp 27 fujitsu microelectronics proprietary and confidential MB86R01 data sheet pin no. jedec pin name process 45 af20 i2c_scl1 46 af21 i2c_sda1 pull up to vdde or pull down to vss through high resistance. 47 af22 int_a[0] 48 af23 ma[8] keep the pin open. 49 af24 ma[12] 52 ae26 ma[7] 53 ad26 ma[3] 54 ac26 ma[1] 55 ab26 mba[1] 57 y26 mdqsn[0] pull down to vss through high resistance. 58 w26 mdqsp[0] 60 u26 mdqsn[1] 61 t26 mdqsp[1] 63 p26 mckn keep the pin open. 64 n26 mckp 66 l26 mdqsn[2] pull down to vss through high resistance. 67 k26 mdqsp[2] 69 h26 mdqsn[3] 70 g26 mdqsp[3] 72 e26 mem_ed[3] 73 d26 mem_ed[7] pull up to vdde or pull down to vss through high resistance. 74 c26 mem_ed[11] 78 a24 mem_ea[1] 79 a23 mem_ea[4] 80 a22 mem_ea[8] 81 a21 mem_ea[12] 82 a20 mem_ea[16] 83 a19 mem_ea[20] 85 a17 mem_xrd 88 a14 tdo keep the pin open. 92 a10 tracedata[3], uart_sin4 pull up to vdde or pull down to vss through high resistance. 94 a8 doutb0[4] keep the pin open. 95 a7 doutg0[2] 96 a6 doutg0[6] 97 a5 dclkin0 pull up to vdde or pull down to vss through high resistance. 99 a3 dclko0 keep the pin open. 101 b2 de0 102 c2 gv0 103 d2 doutb1[5], mem_ed[17], doutg0[1] 104 e2 doutg1[3], mem_ed[21], gpio_pd[7] pull up to vdde or pull down to vss through high resistance. 105 f2 doutg1[7], mem_ed[25], gpio_pd[11] 28 fujitsu microelectronics proprietary and confidential MB86R01 data sheet pin no. jedec pin name process 106 g2 doutr1[5], mem_ed[29], i2s_ws0 pull up to vdde or pull down to vss through high resistance. 108 j2 gv1, dreq[7] 109 k2 vin0[6] 110 l2 vin0[2] 112 n2 vinfid0, gi1[3], mlb_clk 113 p2 usb_avdp connect to vddi. 114 r2 usb_fsdp 115 t2 usb_fsdm pull down to vss through 10k ? resistance. 116 u2 usb_avsf2 connect to vss. 117 v2 usb_mode pull up to vdde or pull down to vss through high resistance. 118 w2 vin1[5], ri1[5], can_tx0 keep the pin open. 119 y2 vin1[2], ri1[2], can_rx1 121 ab2 i2s_sdo2, bi1[6], spi_do, gpio_pd[1] 122 ac2 pwm_o1, bi1[7], gpio_pd[2] 123 ad2 pwm_o0, gi1[2], gpio_pd[3] 125 ae3 ide_xdasp, i2s_ws1 126 ae4 ide_xddmack, reserved (output) 127 ae5 ide_dd[13], can_tx1 128 ae6 ide_dd[9], gpio_pd[21] 129 ae7 ide_dd[5], gpio_pd[17] 130 ae8 ide_dd[1], gpio_pd[13] 131 ae9 ide_da[0], pwm_o0 132 ae10 ide_xdcs[0], reserved (output) 133 ae11 mpx_mode_5[0] pull up to vdde or pull down to vss through high resistance. 135 ae13 ad_vrh0 connect to vss. 136 ae14 ad_vrh1 137 ae15 uart_xrts0 keep the pin open. 138 ae16 uart_xcts0 pull up to vdde or pull down to vss through high resistance. 139 ae17 uart_sout1 keep the pin open. 140 ae18 sd_dat[1] 141 ae19 sd_xmcd pull up to vdde or pull down to vss through high resistance. 142 ae20 i2c_scl0 143 ae21 int_a[3] 144 ae22 mcke_start pull down to vss through high resistance. 145 ae23 ma[13] keep the pin open. 146 ae24 ma[4] 147 ae25 ma[11] 148 ad25 ma[5] 149 ac25 ma[10] 150 ab25 mba[0] 29 fujitsu microelectronics proprietary and confidential MB86R01 data sheet pin no. jedec pin name process 151 aa25 mcke keep the pin open. 152 y25 mdq[2] pull down to vss through high resistance. 153 w25 mdq[0] 154 v25 vref0 connect to ddr vde/2[v]reference voltage. 155 u25 mdq[13] pull down to vss through high resistance. 156 t25 mdq[8] 157 r25 mdq[15] 160 m25 mdq[21] 161 l25 mdq[16] 162 k25 vref1 connect to ddr vde/2[v]reference voltage. 163 j25 mdq[29] pull down to vss through high resistance. 164 h25 mdq[24] 165 g25 mdq[31] 166 f25 mem_ed[0] 167 e25 mem_ed[4] pull up to vdde or pull down to vss through high resistance. 168 d25 mem_ed[8] 169 c25 mem_ed[12] 170 b25 mem_ed[14] 171 b24 mem_ed[15] 172 b23 mem_ea[3] 173 b22 mem_ea[7] 174 b21 mem_ea[11] 175 b20 mem_ea[15] 176 b19 mem_ea[19] 177 b18 mem_ea[23] 178 b17 mem_xwr[1] 179 b16 mem_xcs[4] 183 b12 tms 184 b11 tracedata[0], uart_sout5, pwm_o0 185 b10 tracectl, uart_sout3 keep the pin open. 187 b8 doutb0[5] 188 b7 doutg0[3] 189 b6 doutg0[7] 190 b5 doutr0[4] 192 b3 hsync0 193 c3 vsync0 pull up to vdde or pull down to vss through high resistance. 194 d3 doutb1[4], mem_ed[16], doutg0[0] 195 e3 doutg1[2], mem_ed[20], gpio_pd[6] 196 f3 doutg1[6], mem_ed[24], gpio_pd[10] 197 g3 doutr1[4], mem_ed[28], i2s_sdi0 198 h3 doutr1[7], mem_ed[31], i2s_eclk0 199 j3 vsync1, xdack[6] 30 fujitsu microelectronics proprietary and confidential MB86R01 data sheet pin no. jedec pin name process 200 k3 vin0[7] 201 l3 vin0[3] pull up to vdde or pull down to vss through high resistance. 202 m3 vinvsync0, gi1[5], mlb_data keep the pin open. 203 n3 vinhsync0, gi1[4], mlb_sig 204 p3 usb_avsf1 connect to vss. 205 r3 usb_avdf1 connect to vdde. 206 t3 usb_avsf2 connect to vss. 207 u3 usb_avdf2 connect to vddi. 208 v3 vin1[7], ri1[7], gpio_pd[5] keep the pin open. 209 w3 vin1[4], ri1[4], can_rx0 210 y3 vin1[1], gi1[7], i2s_sck1 211 aa3 vinvsync1, i2s_eclk1 212 ab3 i2s_sdi2, bi1[2], spi_di 213 ac3 ide_diordy, reserved (input) pull up to vdde or pull down to vss through high resistance. 214 ad3 ide_xcblid, i2s_sck1 keep the pin open. 215 ad4 ide_ddmarq, i2s_eclk1 pull up to vdde or pull down to vss through high resistance. 216 ad5 ide_dd[14], can_rx0 keep the pin open. 217 ad6 ide_dd[10], gpio_pd[22] 218 ad7 ide_dd[6], gpio_pd[18] 219 ad8 ide_dd[2], gpio_pd[14] 220 ad9 ide_da[1], pwm_o1 221 ad10 ide_xdior, reserved (output) 222 ad11 mpx_mode_1[1] pull up to vdde or pull down to vss through high resistance. 224 ad13 ad_vin0 connect to vss. 225 ad14 ad_vin1 227 ad16 uart_sout2 keep the pin open. 228 ad17 sd_cmd 229 ad18 sd_dat[2] pull up to vdde or pull down to vss through high resistance. 230 ad19 usb_prtpwr keep the pin open. 231 ad20 i2c_sda0 232 ad21 int_a[1] pull up to vdde or pull down to vss through high resistance. 234 ad23 ma[9] keep the pin open. 235 ad24 ma[6] 236 ac24 ma[2] 237 ab24 mwe 238 aa24 mras 239 y24 mdq[5] pull down to vss through high resistance. 240 w24 mdq[1] 241 v24 mdq[7] 242 u24 mdq[10] 243 t24 mdq[9] 31 fujitsu microelectronics proprietary and confidential MB86R01 data sheet pin no. jedec pin name process 244 r24 mdm[1] pull down to vss through high resistance. 247 m24 mdq[18] 248 l24 mdq[17] 249 k24 mdq[23] 250 j24 mdq[26] 251 h24 mdq[28] 252 g24 mdm[3] 253 f24 mem_ed[1] pull up to vdde or pull down to vss through high resistance. 254 e24 mem_ed[5] 255 d24 mem_ed[9] 256 c24 mem_ed[13] 257 c23 mem_ea[2] 258 c22 mem_ea[6] 259 c21 mem_ea[10] 260 c20 mem_ea[14] 261 c19 mem_ea[18] 262 c18 mem_ea[22] 263 c17 mem_xwr[0] 264 c16 mem_xcs[2] 267 c13 tck 269 c11 tracedata[1], uart_sin5, pwm_o1 270 c10 traceclk, uart_sin3 271 c9 doutb0[2] keep the pin open. 272 c8 doutb0[6] 273 c7 doutg0[4] 274 c6 doutr0[2] 275 c5 doutr0[5] 276 c4 doutr0[7] 277 d4 doutb1[3], mem_xwr[3], doutb0[1] 278 e4 doutb1[7], mem_ed[19], doutr0[1] pull up to vdde or pull down to vss through high resistance. 279 f4 doutg1[5], mem_ed[23], gpio_pd[9] 280 g4 doutr1[3], mem_ed[27], i2s_sdo0 281 h4 doutr1[6], mem_ed[30], i2s_sck0 282 j4 hsync1, dreq[6] 283 k4 de1, xdack[7] keep the pin open. 284 l4 vin0[4] 285 m4 vin0[0] pull up to vdde or pull down to vss through high resistance. 287 p4 usb_avsb connect to vss. 288 r4 usb_avsf2 289 t4 usb_avsf2 292 w4 vin1[3], ri1[3], can_tx1 keep the pin open. 32 fujitsu microelectronics proprietary and confidential MB86R01 data sheet pin no. jedec pin name process 293 y4 vin1[0], gi1[6], i2s_ws1 keep the pin open. 294 aa4 vinhsync1, i2s_sdi1 pull up to vdde or pull down to vss through high resistance. 295 ab4 i2s_ws2, bi1[3], spi_ss keep the pin open. 296 ac4 ide_dintrq, i2s_sdo1 297 ac5 ide_dd[15], can_tx0 298 ac6 ide_dd[11], gpio_pd[23] 299 ac7 ide_dd[7], gpio_pd[19] 300 ac8 ide_dd[3], gpio_pd[15] 301 ac9 ide_da[2], reserved (output) 302 ac10 ide_xdiow, reserved (output) 303 ac11 mpx_mode_1[0] pull up to vdde or pull down to vss through high resistance. 305 ac13 ad_vr0 connect to vss. 306 ac14 ad_vr1 308 ac16 uart_sin2 pull up to vdde or pull down to vss through high resistance. 309 ac17 sd_clk keep the pin open. 310 ac18 sd_dat[3] 312 ac20 int_a[2] pull up to vdde or pull down to vss through high resistance. 313 ac21 ddrtype pull up to vdde through high resistance. 314 ac22 odtcont keep the pin open. 315 ac23 ma[0] 316 ab23 mcs 317 aa23 mcas 318 y23 mdq[3] pull down to vss through high resistance. 319 w23 mdq[4] 320 v23 mdm[0] 321 u23 mdq[11] 322 t23 mdq[12] 323 r23 mdq[14] 324 p23 ocd keep the pin open. 325 n23 odt 326 m23 mdq[19] pull down to vss through high resistance. 327 l23 mdq[20] 328 k23 mdm[2] 329 j23 mdq[27] 330 h23 mdq[25] 331 g23 mdq[30] 332 f23 mem_ed[2] 333 e23 mem_ed[6] pull up to vdde or pull down to vss through high resistance. 334 d23 mem_ed[10] 335 d22 mem_ea[5] 33 fujitsu microelectronics proprietary and confidential MB86R01 data sheet pin no. jedec pin name process 336 d21 mem_ea[9] 337 d20 mem_ea[13] pull up to vdde or pull down to vss through high reistance. 338 d19 mem_ea[17] 339 d18 mem_ea[21] 340 d17 mem_ea[24] 341 d16 mem_xcs[0] 342 d15 mem_rdy 344 d13 tdi 346 d11 tracedata[2], uart_sout4 347 d10 rtck keep the pin open. 348 d9 doutb0[3] 349 d8 doutb0[7] 350 d7 doutg0[5] 351 d6 doutr0[3] 352 d5 doutr0[6] 362 p5 usb_avdb connect to vdde. 363 r5 usb_ext12k pull down to vss through 10k ? resistance. 364 t5 usb_avsf2 connect to vss. 378 ab13 ad_vrl0 379 ab14 ad_vrl1 391 v22 mdq[6] pull down to vss through high resistance. 398 l22 mdq[22] 34 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 7.2.25. unused pin with pin multiplex function in the duplex case pwm, i2s1, and can pins may be duplicated and allocated to external pin depending on pin multiplex function's group combination. in this case, follow the procedure below. pin no. jedec pin multiplex group: pin name process 122 ac2 pin multiplex group #2:pwm_o1 keep the pin open. 123 ad2 pin multiplex group #2:pwm_o0 220 ad9 pin multiplex group #4:pwm_o1 131 ae9 pin multiplex group #4:pwm_o0 269 c11 pin multiplex group #5:pwm_o1 pull down to vss through high resistance. 184 b11 pin multiplex group #5:pwm_o0 118 w2 pin multiplex group #2:can_tx0 keep the pin open. 292 w4 pin multiplex group #2:can_tx1 209 w3 pin multiplex group #2:can_rx0 119 y2 pin multiplex group #2:can_rx1 297 ac5 pin multiplex group #4:can_tx0 127 ae5 pin multiplex group #4:can_tx1 216 ad5 pin multiplex group #4:can_rx0 30 af5 pin multiplex group #4:can_rx1 210 y3 pin multiplex group #2:i2s_sck1 293 y4 pin multiplex group #2:i2s_ws1 211 aa3 pin multiplex group #2:i2s_eclk1 294 aa4 pin multiplex group #2:i2s_sdi1 pull down to vss through high resistance. 22 ab1 pin multiplex group #2:i2s_sdo1 keep the pin open. 28 af3 pin multiplex group #4:i2s_sdi1 pull down to vss through high resistance. 125 ae3 pin multiplex group #4:i2s_ws1 keep the pin open. 215 ad4 pin multiplex group #4:i2s_eclk1 pull down to vss through high resistance. 214 ad3 pin multiplex group #4:i2s_sck1 keep the pin open. 296 ac4 pin multiplex group #4:i2s_sdo1 35 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8. electrical characteristics 8.1. maximum ratings table 8-1, table 8-2, and table 8-3 show the maximum ratings. t able 8-1 maximum ratings parameter symbol rating unit supply voltage vddi, pllvdd vdde ddrvde -0.5 to 1.8 (*1) -0.5 to 4.0 (*2) -0.5 to 2.5 (*3) v input voltage v i -0.5 to vddi + 0.5 (< 1.8v) -0.5 to vdde + 0.5 (< 4.0v) -0.5 to ddrvde + 0.5 (< 2.5v) v output voltage v o -0.5 to vddi + 0.5 (< 1.8v) -0.5 to vdde + 0.5 (< 4.0v) -0.5 to ddrvde + 0.5 (< 2.5v) v storage temperature t st -55 to 125 c junction temperature t j -40 to 125 c power consumption p d 1.5 w supply current i d 1.2v: 690.1 (*4) 1.8v: 508 (*4) 3.3v: 125.3 (*4) ma *1: power supply for internal part or pll *2: power supply for i/o part *3: power supply for sstl_18 i/o part *4: current specification necessary for each voltage power supply note: ? applying stress exceeding the maximum ratings ( voltage, current, temperature, etc.) may cause damage to semiconductor devices. never exceed the ratings above. ? since thermal destruction of elemen ts might occur, do not connect ic output or i/o pin directly, or connect them to v dd or v ss directly, except the pin designed output timing to prevent such incident. ? provide esd protection, such as grounding when handling the product; otherwise externally-charged electric charge flows into the ic and discha rges, which may cause circuit destruction. ? applying voltage higher than v dd or lower than v ss to i/o pins of cmos ic, or applying voltage higher than the ratings between v dd and v ss may cause latch up. the latch up increases supply current, resulting in thermal destruction of elements. when handling the product, never exceed the maximum ratings. 36 fujitsu microelectronics proprietary and confidential MB86R01 data sheet table 8-2 adc maximum ratings parameter symbol rating unit supply voltage ad_avd0 -0.5 to 4.0 v input voltage ad_vrh0 ad_vrh1 ad_vrl0 ad_vrl1 ad_vin0 ad_vin1 -0.5 to vdde + 0.5 (< 4.0v) v output voltage ad_vr0 ad_vr1 -0.5 to vdde + 0.5 (< 4.0v) v junction temperature t j -40 to 125 c the maximum ratings of usb phy are shown in table 8-3. t able 8-3 usb2.0 maximum ratings parameter symbol rating unit usb_avdf1 usb_avdb v ss --0.5 to 4.0 v supply voltage usb_avdf2 usb_avdp v ss --0.5 to 1.8 v junction temperature t j -40 to 125 c usb_avdf1 usb_avdb total 37.5 ma usb_avdf2 19.2 ma supply current usb_avdp 13.0 ma the maximum ratings are the limits that must not be exceeded. as long as usb phy is used within the range predetermined in the maximum ratings, it never suffers permanent damage. however, this does not assure normal logic operation. 37 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.2. recommended operating conditions table 8-4 3.3v standard cmos i/o recommended opera ting conditions rating parameter symbol min. typ. max. unit power supply voltage vdde vddi, pllvdd 3.0 1.1 3.3 1.2 3.6 1.3 v input voltage (high level) 3.3v cmos vih 2.0 ? vdde + 0.3 v input voltage (low level) 3.3v cmos vil -0.3 ? 0.8 v operating ambient temperature t a -40 ? 85 c junction temperature t j -40 ? 125 c table 8-5 sstl_18 recommended operating conditions parameter symbol min. typ. max. unit vde (ddrvde) 1.7 1.8 1.9 v power supply voltage vddi 1.10 1.20 1.30 v junction temperature t j -40 ? 125 c the recommended operating conditions for the sta ndard sstl_18 (excerpted from jesd8-15a). table 8-6 usb2.0 recommended operating conditions value parameter symbol min. typ. max. unit usb_avdf1 usb_avdb 3.0 3.3 3.6 v usb_avdf2 1.1 1.2 1.3 v supply voltage usb_avdp 1.1 1.2 1.3 v junction temperature t j -40 ? 125 c clock to be input to usb_cr yclk48 should meet followings: ? 48mhz100ppm clock ? 100ps or less jitter note: the recommended operating conditions are primarily intended to assure the normal operation of semiconductor device. the values of electrical characteristics are gu aranteed under the requirements above, so use the product accordingly. using the product without observing the conditions may affect the product's reliability. performance of this product is not guaranteed us ing under the unspecified conditions and unspecified combination of logic. be sure to contact fujitsu when using the product under such conditions. 38 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.3. precautions at power on 8.3.1. recommended power on/off sequence follow the power on/off sequence as shown below: 39 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.3.2. power on reset v dde (external) ddrvde (dram) xrst x trst note: clock is just an image, not the actual one. clk input "l" when power-on input clock immediately after power-on pll lockup time v ddi (internal) input "l" when power-on 2 s or more xsrst output "l" when power-on for inputting the external signal to xsrst, input xsrst after changing xrst from "l" to "h". xtrst input is required only when MB86R01 is in dft mode(jtagsel=?h?). figure 8-3 power on sequence input xrst pin to low when power-on. keep xrst pin high after setting to low level for 2 s or more. access the other registers or memory controller after pll lockup time. when MB86R01 is in dft mode, xtrst should be input as well as xrst. 40 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.4. dc characteristics 8.4.1. 3.3v standard cmos i/o table 8-7 shows 3.3v standard cmos i/o dc characteristics. table 8-7 standard cmos i/o dc characteristics measurement condition: vdde = 3.3 0.3v, vss = 0v, t j = -40 to 125 c rating parameter symbol condition min. typ. max. unit h level input voltage vih 2.0 ? vdde + 0.3 v l level input voltage vil -0.3 ? 0.8 v h level output voltage voh ioh = -100 a vdde - 0.2 ? vdde v l level output voltage vol iol = 100 a 0 ? 0.2 v driving capability 1 ioh = 4ma driving capability 2 ioh = 6ma h level output v-i characteristic ? driving capability 3 ioh = 8ma ? driving capability 1 iol = 4ma driving capability 2 iol = 6ma l level output v-i characteristic ? driving capability 3 iol = 8ma see figure 8-4, figure 8-5, and figure 8-6 chara cteristics ? input leakage current il ? ? 4 a driving capabilities 1 to 3 in the table above indicate the following external pins: driving capability 1: tdo, mem_ea[24: 1], mem_ed[15:0], mem_rdy, mem_xcs0, mem_xcs2, mem_xcs4, mem_xrd, mem_xwr0, mem_xwr1 driving capability 2: vinhsync0, vinvsync0, i2s_eclk2, i2s_sck2, i2s_sdo2,i2s_ws2, ide_dd[15:0], ide_dintrq, ide_xcblid, ide_xdasp, pwm_o0, pwm_o1, vin10-7, vinfid1, doutb1[7:2], doutg1[7:2], doutr1[7:2], gv1, hsync0, hsync1, sd_cmd, sd_dat[3:0], traceclk, traced ata[3:0], vin0[7:0], vsync0, vsync1, xsrst, de0, de1, doutb0[7:2], doutg0[7:2], doutr0[7:2], gv0, ide_csel, ide_da[2:0], ide_xdcs[1:0], ide_xddmack, ide_xdior, ide_xdiow, ide_xdreset, rtck, sd_clk, tracectl, uart_sout[2 :0], uart_xrts0, usb_prtpwr driving capability 3: dclko[1:0] 41 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.4.1.1. 3.3v standard cmos i/o v-i char acteristic (driving cap ability 1) conditions min: process = slow t j = 125 c vdde = 3.0 v typ: process = typical t j = 25 c vdde = 3.3 v max: process = fast t j = -40 c vdde = 3.6 v figure 8-4 3.3v standard cmos i/o v-i characteristic (driving capability 1) 42 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.4.1.2. 3.3v standard cmos i/o v-i char acteristic (driving cap ability 2) conditions min: process = slow t j = 125 c vdde = 3.0 v typ: process = typical t j = 25 c vdde = 3.3 v max: process = fast t j = -40 c vdde = 3.6 v figure 8-5 3.3v standard cmos i/o v-i characteristic (driving capability 2) 43 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.4.1.3. 3.3v standard cmos i/o v-i char acteristic s (driving capability 3) conditions min: process = slow t j = 125 c vdde = 3.0 v typ: process = typical t j = 25 c vdde = 3.3 v max: process = fast t j = -40 c vdde = 3.6 v figure 8-6 3.3 v standard cmos i/o v- i characteristic (driving capability 3) 44 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.4.2. ddr2sdram if i/o (sstl_18) sstl_18 dc characteristics (excerpted from jesd8-15a). table 8-8 sstl18 input dc logic levels (single ended) symbol parameter min. max. unit vih (dc) dc input logic high vref + 125 vddq + 300 mv vil (dc) dc input logic low -300 vref - 125 mv table 8-9 sstl18 input ac logic levels (single ended) symbol parameter min. max. unit vih (ac) ac input logic high vref + 250 ? mv vil (ac) ac input logic low ? vref - 250 mv table 8-10 sstl18 input ac test conditions (single ended) symbol condition value unit vref input reference voltage 0.5 vddq v vswing (max.) input single maximum peak to peak swing 1.0 v slew input single minimum slew rate 1.0 v/ns table 8-11 sstl18 input dc logic levels (differential ended) symbol parameter min. max. unit vin (dc) dc input signal voltage -300 vddq + 300 mv vid (dc) dc differential input voltage 250 vddq + 600 mv table 8-12 sstl18 input ac logic levels (differential ended) symbol parameter min. max. unit vid (ac) ac differential input voltage 500 vddq + 600 mv vix (ac) ac differential cross point voltage 0.5 vddq - 175 0.5 vddq + 175 mv table 8-13 sstl18 input ac test conditions (differential ended) symbol parameter min. max. unit vr input timing measurement reference level vix (cross point) v vswing input signal peak to peak swing voltage ? 1.0 v slew input signal slew rate 1.0 ? v/ns table 8-14 sstl18 outp ut dc current drive symbol parameter min. max. unit notes ioh (dc) output minimum source dc current -11.4 (*3) ? ma (*1) iol (dc) output minimum sink dc current 11.4 (*3) ? ma (*2) *1: vddq = 1.7v, vout = 1420mv *2: vddq = 1.7v, vout = 280mv *3: the value is different from jesd8-15a. (jesd8-15a: 13.4ma) 45 fujitsu microelectronics proprietary and confidential MB86R01 data sheet table 8-15 sstl18 diffe rential ac parameters symbol parameter min. max. unit vox ac differential cross point volta ge 0.5 vddq - 125 0.5 vddq + 125 mv note: external pin for ddr2sdram io buffer is as follows. mdqsp[3:0], mdqsn[3:0], mdm[3:0], mdq[31:0], mckp, mckn, ma[13:0], mba[1:0], mcas, mcke, mcs, mras, mwe, odtcont, ocd, odt, vref0, vref1 46 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.4.3. adc table 8-16 recommended operating conditions value parameter symbol min. typ. max. unit power supply voltage ad_avd0 2.70 3.00 3.60 v reference voltage (h) ad_vrh0 ad_vrh1 ad_avd0*0.75 ? ad_avd0 v reference voltage (l) ad_vrl0 ad_vrl1 v ss (*1) ? ad_avd0*0.25 v decoupling capacitor ad_vr0 (*2) ad_vr1 (*2) 0.05 ? ? f analog input voltage ad_vin0 ad_vin1 ad_vrl0 ad_vrl1 ? ad_vrh0 ad_vrh1 v analog input frequency ad_vin0 ad_vin1 0 ? 500 khz note: *1: v ss = ad_avs1 (analogue gnd) *2: in the case that vr is decoupled with avs by d ecoupling capacitor, a/d outputs incorrect result at immediately after power-on or at the resumption from power down mode. because charge current for decoupling capacitors is supplied through the re ference resistance, it takes about 2ms to get correct result (it is the case decoupling capacitor is 0.1f.). table 8-17 adc characteristics (vdd = 1.2v, avd = 3.0v, fs = 100ks/s, fc = 1.4mhz, fvin = 1 khz, t a = 25c (*1)) value parameter symbol min. typ. max. unit ? 0.8 1.2 ma supply current (included reference current) ad_avd0 -1 ? 50 a ? ad_avd0/2 ? v reference voltage (m) ad_vr0 ad_vr1 -3 ? 3 % reference resistance ad_vrh0 ad_vrh1 ad_vrl0 ad_vrl1 7.3 9 10.7 k ? zero transition voltage (*2) typ. -20 ad_vrl0+1lsb ad_vrl1+1lsb typ. +20 mv full scale transition voltage (*2) typ. -20 ad_vrh0-1lsb ad_vrh1-1lsb typ. +20 mv integral non linearity (*3) -2.0 ? +2.0 lsb differential non linearity (*3) -1.5 ? +1.5 lsb *1: vr is connected to avs with decoupling capacitor (0.1f). unique voltage is supplied to vrh and vrl by voltage source. *2: vzt and vfst are dependent on ch ip layout and wiring resistance. *3: 1lsb = (vfst-vzt)/1022, inln = ((1lsbxn + vz t) - vn)/1lsb, dnln = (vn + 1 -vn)/1lsb - 1 47 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.4.4. i 2 c bus fast mode i/o table 8-18 i 2 c i/o dc characteristics standard mode fast mode (*1) parameter & condition symbol min. max. min. max. unit "l" level input voltage vil -0.5 0.3 vdde -0.5 0.3 vdde v "h" level input voltage vih 0.7 vdde (*2) 0.7 vdde (*2) v schmitt trigger hysteresis vdde > 2[v] vhys n/a n/a 0.05 vdde ? v "l" level output voltage sink current 3[ma] vdde > 2[v] vol1 0 0.4 0 0.4 v output slew rate (tfall) bus capacitance 10[pf] ~ 400[pf] vih (min.) to vil (max.) tof ? 250 20 + 0.1cb (*3) 250 ns data line leakage input voltage 0.1 ~ 0.9 vdde (max.) ii -10 10 -10 10 a i/o pin capacitance ci ? 10 ? 10 pf *1: the i 2 c bus fast mode i/o buffer is downw ard compatible with standard mode. *2: 90nm technology: complies with the maximum ratings 4[v]. *3: cb: capacitance for 1 bus line (unit: pf). *4: the i 2 c bus fast mode i/o buffer itself has no function to prevent spike of 50ns p ulse width (max.). therefore, provide any input filter to prevent spike for bot h internal and external semiconductor device. note: external pin for i 2 c io buffer is as follows. i2c_scl0, i2c_sda0, i2c_scl1, i2c_sda1 48 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.4.4.1. i 2 c io v-1 characteristic figure voltage (v) current (a) figure 8-7 i 2 c v-i characteristic figure 49 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.4.5. usb2.0 table 8-19 recommended oper ating conditions (high-speed) value parameter symbol min. typ. max. unit input levels for high-speed: high-speed squelch detection threshold (differential signal amplitude) vhssq 100 ? 200 mv high-speed disconnect detection threshold (differential signal amplitude) vhsdsc 525 ? 625 mv high-speed differential input signaling levels (this spec is base d on "template 6") 150 (the absolute value) ? ? mv high-speed data signaling common mode voltage range (guideline for receiver) vhscm -50 ? 500 mv output levels for high-speed: high-speed idle level vhsoi -10.0 ? 10.0 mv high-speed data signaling high vhsoh 360 ? 440 mv high-speed data signaling low vhsol -10.0 ? 10.0 mv chirp j level (differential voltage) vchirpj 700 ? 1100 mv chirp k level (differential voltage) vchirpk -900 ? -500 mv terminations in high-speed: termination voltage in high-speed vhsterm -10 ? 10 mv table 8-20 recommended operating conditions (full-speed/low-speed) value parameter symbol min. typ. max. unit input levels for full-speed/low-speed: high (driving) vih 2.0 ? ? v high (floating) vihz 2.7 ? 3.6 v low vil ? ? 0.8 v differential input sensitivity vdi 0.2 ? ? v differential common mode range vcm 0.8 ? 2.5 v output levels for full-speed/low-speed: low vol 0.0 ? 0.3 v high (driven) voh 2.8 ? 3.6 v se1 vose1 0.8 ? ? v output signal crossover voltage vcrs 1.3 ? 2.0 v input capacitance for full-speed/low-speed: downstream facing port (being shared with upstream facing port at device mode, so the less value is selected as the maximum spec) cind (cinub) ? ? 100 pf transceiver edge rate contro l capacitance cedge ? ? 75 pf terminations in full-speed/low-speed: bus pull-up resistor on upstream port (idle bus) (this is used only in the device mode (hostmode = "0" setting).) rpui 0.9 ? 1.575 k bus pull-up resistor on upstream port (upstream port receiving) (this is used only in the device mode (hostmode = "0" setting).) rpua 1.425 ? 3.090 k input impedance exclusive of pull-up/pull-down zinp 300 ? ? k termination voltage on upstream port pull-up vterm 3.0 ? 3.6 v 50 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.5. ac characteristic in this chapter, the ac timing of external ports is described. 8.5.1. memory controller signal timing table 8-21 memory controller ac timing value signal name symbol description min typ max unit mem_xcs0 mem_xcs2 mem_xcs4 t cso chip select dela y time ? ? 10 ns mem_ea[24:1] t ao address delay time ? ? 11 ns t do data output delay time ? ? 11 ns t doz data output hiz time ? ? 12 ns t dsr sram/nor flash data setup time 12 ? ? ns t dhr sram/nor flash data hold time 0 ? ? ns t dsp nor flash page read da ta setup time 13 ? ? ns mem_ed[31:0] t dhp nor flash page read data hold time 0 ? ? ns mem_xrd t rdo xrd delay time ? ? 10 ns mem_xwr[3:0] t wro xwr delay time ? ? 10 ns standard clock of output de lay is internal clock. standard clock of mem_rdy is internal clock. 51 fujitsu microelectronics proprietary and confidential MB86R01 data sheet figure 8-8 sram/nor flash read figure 8-9 sram/nor flash write 52 fujitsu microelectronics proprietary and confidential MB86R01 data sheet figure 8-10 low speed device read internal clk mem_xcs0 mem_xcs2 mem_xcs4 mem_ea[24:1] mem_xwr[1:0] mem_ed[31:0] t cso t ao mem_rdy t wro t wro t do t do x t cso t ao t do min 2cycle(internal clk) + t wro min 0[ns] figure 8-11 low speed device write 53 fujitsu microelectronics proprietary and confidential MB86R01 data sheet figure 8-12 nor flash page read 54 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.5.2. ddr2sdram if this is able to connect with ddr2 sdram which is in conformance with ddr2-400 in the jedec (jesd79-2c.) timing regulation is described below, and output load condition is according to the pcb design guideline. table 8-22 write spec (1 an d 2): ck-cmd/add and ck-dqs criteria value (*1) item symbol spec formula min. typ. max. unit cmd/add setup vali d-data from ck tvd_setup_cmd (tck/2) - 828 2172 ? ? ps cmd/add hold vali d-data from ck tvd_hold_cmd (tck/2) - 545 2455 ? ? ps skew between dqs vs. ck tskew_dqs_ck not tck dependent -1083 ? 772 ps *1: spec for tck = 6ns (333mbps) is indicated table 8-23 write spec (3): dq-dqs criteria value (*1) item symbol spec formula min. typ. max. unit dq/dm setup valid-data from dqs tvd_setup_dq tck/4) - 884 616 ? ? ps dq/dm hold valid-data from dqs tvd_hold_dq tck/4) - 776 724 ? ? ps *1: spec for tck = 6ns (333mbps) is indicated table 8-24 read spec (1): dq-dqs criteria value (*1) item symbol spec formula min. typ. max. unit tsetup dq from dqs tsetup_dq - (0.1875*tck ? 208 ) -917 ? ? ps thold dq from dqs thold_dq 0.1875*tck + 503 1628 ? ? ps *1: spec for tck = 6ns (333mbps) is indicated table 8-25 read spec (2): dq-r.t.t (roundtrip time) criteria value (*1) item symbol spec formula min. typ. max. unit dqs roundtriptime @cl = 3 (ck_out dram dqs_in) trtt_dqs 55 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.5.2.1. ddr2sdram if timing diagram figure 8-13 timing regulation point ddr2 sdram (ddr2-400) ck cmd/ad dq dqs MB86R01 timing regulation point ddr2c * external load condition: pcb design guideline 56 fujitsu microelectronics proprietary and confidential MB86R01 data sheet figure 8-14 write spec (1 and 2): ck-cmd/add and ck-dqs figure 8-15 write spec (3): dq-dqs ck_out /ck_out tskew_dqs_ck cmd/add_out tvd_setup_cmd tvd_hold_cmd dqs_out tskew_dqs_ck valid data tck = 6ns@166mhz dqs_out dq_out dm_out tvd_hold_dq valid data2 valid data1 valid data0 valid data3 tvd_setup_dq tck = 6ns@166mhz 57 fujitsu microelectronics proprietary and confidential MB86R01 data sheet figure 8-16 read spec (1): dq-dqs figure 8-17 read spec (2): dqs-r.t.t (roundtrip time) c k_ ou tck = 6ns@166mhz dqs_in@delay min dqs_in@delay max trtt_dqs@min trtt_dqs@max cl = 3 or 3 dqs_in dq_in tsetup_dq tck = 6ns@166mhz thold_dq thold_dq tsetup_dq 58 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.5.3. gpio signal timing table 8-26 ac timing value signal symbol description min. typ. max. unit t do data output delay time ? ? 13 ns gpio_pd[23:0] t dw input data-width a ? ? ns internal clock is the standard of output delay. a indicates apb bus clock cycle, and it is different from the output delay sta ndard clock. internal clk gpio_pd[23:0] input t do t dw output figure 8-18 gpio timings 59 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.5.4. pwm signal timing 8.5.4.1. output signal table 8-27 ac timing of ide data input signal value signal symbol description min. typ. max. unit pwm_o0 t0 output delay of pwm_o0 based on apb- busclock 2.0 ? 14.0 ns pwm_o1 t1 output delay of pwm_o1 based on apb- busclock 2.0 ? 14.0 ns pwm_o0 apb-busclock t0 pwm_o1 t1 figure 8-19 pwm output timing 60 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.5.5. gdc display signal timing 8.5.5.1. clock table 8-28 ac timing of video interface clock signal value signal symbol description min. typ. max. unit fdclki0 dclki frequency ? ? 80 mhz thdclki0 dclki h width 5 ? ? ns dclki0 tldclki0 dclki l width 5 ? ? ns fdclki1 dclki frequency ? ? 80 mhz thdclki1 dclki h width 5 ? ? ns dclki1 tldclki1 dclki l width 5 ? ? ns dclk (internal) tldclk0 dclk frequency (*1) ? ? 80 mhz dclk (internal) tldclk1 dclk frequency (*1) ? ? 80 mhz dclko0 fdclko dclko frequency ? ? 80 mhz dclko1 fdclko dclko frequency ? ? 80 mhz *1: internal display clock of pll synchr onization mode is generated by division of internal pll in the display clock prescaler. *2: dclki or internal display clock of pll is output. 8.5.5.2. input signal 1) applied the signal only in pll synchronization mode (cks = 0) (reference clock = clock output from internal pll) table 8-29 ac timing of vi deo interface input signal (1) value signal symbol description min. typ. max. unit hsync0 (i) twhsync0 hsync input pulse width 3.0 ? ? clock hsync1 (i) twvsync1 vsync input pulse width 3.0 ? ? clock vsync0 (i) twvsync vsync input pulse width 1 ? ? hsync vsync1 (i) twvsync vsync input pulse width 1 ? ? hsync 2) applied the signal only in dclki synchronization mode (cks = 1) (reference clock = dclki) table 8-30 ac timing of vi deo interface input signal (2) value signal symbol description min. typ. max. unit twhsync0 hsync input pulse width 3.0 ? ? clock tshsync0 hsync input setup time 6.0 ? ? ns hsync0 (i) thhsync0 hsync input hold time 1.0 ? ? ns twhsync1 hsync input pulse width 3.0 ? ? clock tshsync1 hsync input setup time 6.0 ? ? ns hsync1 (i) thhsync1 hsync input hold time 1.0 ? ? ns vsync0 (i) twvsync0 vsync input pulse width 1 ? ? hsync vsync1 (i) twvsync1 vsync input pulse width 1 ? ? hsync 61 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.5.5.3. output signal table 8-31 ac timing of video interface input signal value signal symbol description min. typ. max. unit doutr0[5:0], doutg0[5:0], doutb0[5:0] tdrgb0 rgb output delay time 0 ? 5.5 ns doutr1[5:0], doutg1[5:0], doutb1[5:0] tdrgb1 rgb output delay time 0 ? 5.5 ns hsync0 (o) tdhsync0 hsync output delay time 0 ? 5.5 ns hsync1 (o) tdhsync1 hsync output delay time 0 ? 5.5 ns vsync0 (o) tdvsync0 vsync output delay time 0 ? 5.5 ns vsync1 (o) tdvsync1 vsync output delay time 0 ? 5.5 ns csync0 tdcsync0 csync output delay time 0 ? 5.5 ns csync1 tdcsync1 csync output delay time 0 ? 5.5 ns gv0 tdgv0 gv output delay time 0 ? 5.5 ns gv1 tdgv1 gv output delay time 0 ? 5.5 ns note: if hold time is deficient, inverting dclko clock is recommended. twvsync n dclk i n hsync n (i) ts h s yn c n thhsync n thdclki n tldclki n 1/fdclki n vsync n (i) ts vs y nc n thvsync n twhsync n figure 8-20 display input signal timing 62 fujitsu microelectronics proprietary and confidential MB86R01 data sheet dclko n (inverted) dclko n hsync n (o) 1/fdclk o n vsync n (o) doutr n [5:0] doutg n [5:0] doutb n [5:0] tddrgb n csync n gv n tdhsync n tdvsync n tdcsync n tdgv n figure 8-21 display output signal timing there is no definition of ac ch aracteristics about analog signal. 63 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.5.6. gdc video capture signal timing 8.5.6.1. clock table 8-32 ac timing of vide o capture interface clock signal value signal symbol description min. typ. max. unit f cclk capture clock frequency ? ? 80 mhz t hcclk capture clock h width 3 ? ? ns cclk0, cclk1 t lcclk capture clock l width 3 ? ? ns note: it depends on the resolution of the video source. 8.5.6.2. input signal table 8-33 ac timing of vide o capture interface input signal value signal symbol description min. typ. max. unit t svi input setup time 6 ? ? ns vin0[7:0], vin1[7:0] t hvi input hold time 1 ? ? ns t sri input setup time 6 ? ? ns ri1[7:2] t hri input hold time 1 ? ? ns t sgi input setup time 6 ? ? ns gi1[7:2] t hgi input hold time 1 ? ? ns t sbi input setup time 6 ? ? ns bi1[7:2] t hbi input hold time 1 ? ? ns t shsi input setup time 6 ? ? ns vinhsync0, vinhsync1 t hhsi input hold time 1 ? ? ns t svsi input setup time 6 ? ? ns vinvsync0, vinvsync1 t hvsi input hold time 1 ? ? ns t sfi input setup time 6 ? ? ns vinfid0, vinfid1 t hfi input hold time 1 ? ? ns figure 8-22 video capture clock input signal timing 1/f cclk t lcclk t hcclk cclk0, cclk1 64 fujitsu microelectronics proprietary and confidential MB86R01 data sheet t svi t sri t sgi t sbi t shsi t svsi t sfi vin0/1 t hvi t hri t hgi t hbi t hhsi t hvsi t hfi ri,gi,bi vinhsync0/1 vinvsync0/1 cclk0/1 vinfid0/1 figure 8-23 video capture input signal timing 65 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.5.7. i2s signal timing table 8-34 timing requirements value signal symbol description min. typ. max. unit t scyc operating frequency, i2s_sckx (slave mode) ? ? 0.5*b mhz t shw pulse duration, i2s_sckx high (slave mode) 0.45*t ? 0.55*t ns i2s_sckx t slw pulse duration, i2s_sckx low (slave mode) 0.45*t ? 0.55*t ns t sfi setup time, external i2s_wsx high before i2s_sckx low (slave mode) 8 ? ? ns i2s_wsx t hfi hold time, external i2s_wsx high after i2s_sckx low (slave mode) 4 ? ? ns setup time, i2s_sdix valid before i2s_sckx low (master mode) 8 ? ? ns t sdi setup time, i2s_sdix valid before i2s_sckx low (slave mode) 8 ? ? ns hold time, i2s_sdix valid after i2s_sckx low (master mode) 4 ? ? ns i2s_sdix t hdi hold time, i2s_sdix valid after i2s_sckx low (slave mode) 4 ? ? ns b indicates ahb bus clock frequency. t indicates i2s_sckx cycle. table 8-35 switching characteristics value signal symbol description min. typ. max. unit t mcyc operating frequency, i2s_sckx (master mode) ? ? 0.5*b mhz t mhw pulse duration, i2s_sckx high (master mode) 0.45*t ? 0.55*t ns i2s_sckx t mlw pulse duration, i2s_sckx low (master mode) 0.45*t ? 0.55*t ns i2s_wsx t dfs delay time, i2s_sckx high to i2s _ wsx transition (master mode) -12 ? 12 ns delay time, i2s_sckx high to i2s _ sdox valid except the first bit of transmit frame. (master mode) -12 ? 17 ns t ddo delay time, i2s_sckx high to i2s _ sdox valid except the first bit of transmit frame. (slave mode) 3 ? 32 ns i2s_sdox t dfb1 delay time, i2s_sckx high to the first bit of a transmit frame when fsph bit of i2sx_cntreg register is 1. (master mode) -14 ? 17 ns b indicates ahb bus clock frequency. t indicates i2s_sckx cycle. 66 fujitsu microelectronics proprietary and confidential MB86R01 data sheet figure 8-24 master mode timing i2s_sckx i2s_wsx (fsph=0, fsln=0) i2s_wsx (fsph=1,fsln=0) i2s_wsx (fsph=0, fsln=1) i2s_wsx (fsph=1, fsln=1) i2s_sdox i2s_sdix t dfb1 t sdi t hd i t sdi t hd i t ddo t sfi t hfi t sfi t hfi t sfi t sfi t scyc t shw t slw figure 8-25 slave mode timing fsph is bit 2 of i2sx_cntreg register. fsln is bit 1 of i2sx_cntreg register. i2s_sckx i2s_wsx (fsph=0, fsln=0) i2s_wsx (fsph=1, fsln=0) i2s_wsx (fsph=0, fsln=1) i2s_wsx (fsph=1, fsln=1) i2s_sdox i2s_sdix t ddo t dfs t dfs t dfs t dfs t dfs t dfb1 t dfs t dfs t sdi t hd i t sdi t hd i t dfs t mcyc t mhw t mlw 67 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.5.8. uart signal timing table 8-36 ac timing value signal symbol description min. typ. max. unit uart_sout0 uart_sout1 uart_sout2 uart_sout3 uart_sout4 uart_sout5 t do data output delay time ? ? 12 ns uart_sin0 uart_sin1 uart_sin2 uart_sin3 uart_sin4 uart_sin5 t dw input data width 16*a ? ? ns uart_xrts0 t rtso xrts output delay time ? ? 11 ns uart_xcts0 t ctsw input xcts data width a ? ? ns internal clock is the standard of output delay. a indicates apb bus clock cycle, and it is different from the output delay sta ndard clock. internal clk uart_sout0 uart_sout1 uart_sout2 uart_sout3 uart_sout4 uart_sout5 uart_sin0 uart_sin1 uart_sin2 uart_sin3 uart_sin4 uart_sin5 t do t dw n? n? uart_xcts0 t ctsw t rtso uart_xrts0 n? n? figure 8-26 uart timing 68 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.5.9. i 2 c bus timing table 8-37 ac timing of i 2 c signal value signal symbol description min. typ. max. unit normal mode 250 (*1) ? ? ns t s2sdai sdai setup time high-speed mode 100 (*1) ? ? ns normal mode 0.0 (*1) ? ? ns t h2sdai sdai hold time high-speed mode 0.0 (*1) ? ? ns normal mode 4.7 (*1) ? ? s i2c_sda0 i2c_sda1 t wbfi bus free time high-speed mode 1.3 (*1) ? ? s normal mode 1.0 (*1) ? ? s t cscli scli cycle time high-speed mode 2.5 (*1) ? ? s normal mode 4.0 (*1) ? ? s t whscli scli h width high-speed mode 0.6 (*1) ? ? s normal mode 4.7 (*1) ? ? s t wlscli scli l width high-speed mode 1.3 (*1) ? ? s normal mode 2*m + 2 (*2) ? ? pclk (*3) t csclo sclo cycle time high-speed mode int (1.5*m) + 2 (*2) ? ? pclk (*3) normal mode m + 2 (*2) ? ? pclk (*3) t whsclo sclo h width high-speed mode int (0.5*m) + 2 (*2) ? ? pclk (*3) normal mode m (*2) ? ? pclk (*3) t wlsclo sclo l width high-speed mode m (*2) ? ? pclk (*3) normal mode 4.0 (*2) ? ? s t s2scli scli setup time high-speed mode 0.6 (*2) ? ? s normal mode 4.7 (*2) ? ? s i2c_scl0 i2c_scl1 t h2scli scli hold time high-speed mode 1.3 (*2) ? ? s *1: i 2 c bus specification value *2: see i 2 c bus interface's clock control register (i2cxccr) of the MB86R01 lsi product specifications for the "m" value *3: pclk = apb bus clock cycle i2c_sda0(in) i2c_sda1(in) i2c_sda0(out) i2c_sda1(out) i2c_scl0(in) i2c_scl1(in) i2c_scl0(out) i2c_scl1(out) d6 d7 t s2sdai t h2sdai t s2scli t h2scli d4 d5 d2 d3 d0 d1 ack start restart t whscli t wlscli t cscli d6 d7 t h2sdao t s2sclo t h2sclo d4 d5 d2 d3 d0 d1 ack start restart t whsclo t wlsclo t csclo stop t s2sclo stop t s2scli t h2scli t wbfi t h2sclo figure 8-27 i 2 c access timing 69 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.5.10. spi signal timing table 8-38 spi ac timing value signal symbol description min. typ. max. unit spi_sck t cyc operating frequency ? ? 0.5*a mhz t sdi setup time, spi_di valid before spi_sck 15 ? ? ns spi_di t hdi hold time, spi_di valid after spi_sck 15 ? ? ns spi_do t do delay time, spi_sck -2 ? 5 ns spi_ss t sso delay time, spi_sck -2 ? 5 ns a indicates apb bus clock frequency. spi_sck spi_di t do t sdi spi_do t sso spi_ss t hdi spi_sck t cyc figure 8-28 spi timing polarity of spi_sck is determined by the register setting. 70 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.5.11. can signal timing table 8-39 can ac timing value signal symbol description min. typ. max. unit can_tx0 can_tx1 t do data output delay time ? ? 17 ns can_rx0 can_rx1 t dw input data width 1000 ? ? ns internal clock is the standard of output delay. internal clk can_tx0 can_tx1 can_rx0 can_rx1 t do t dw n? n? figure 8-29 can timing 71 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.5.12. medialb signal timing 8.5.12.1. medialb ac spec type a ground = 0v; load capacitance = 60pf; medialb speed = 256fs or 512fs; fs = 48khz; all timing parameters specified from the valid voltage thre shold as listed below; unless otherwise noted. 8.5.12.1.1. clock table 8-40 ac timing of clock signal value signal symbol description min. typ. max. unit comment f mck mlbclk operating frequency (*1) 11.264 ? ? ? 22.5792 ? ? ? 24.6272 mhz 256xfs at 44.0khz 512xfs at 44.1khz 512xfs at 48.1khz t mckr mlbclk rising time ? ? 3 ns v il to v ih t mckf mlbclk falling time ? ? 3 ns v ih to v il t mckc mlbclk cycle time ? ? 81 40 ? ? ns 256xfs 512xfs t mckl mlbclk low time 30 14 37 17 ? ? ns 256xfs 512xfs t mckh mlbclk high time 30 14 38 17 ? ? ns 256xfs 512xfs mlbclk t mpwv mlbclk pulse width variation ? ? 2 ns pp (*2) *1: the controller can shut off mlbclk to place medialb in a low-power state. *2: pulse width variation is measured at 1.25v by triggering on one edge of mlbclk and measuring the spread on the other edge, measured in ns peak-to-peak (pp). 8.5.12.1.2. input signal table 8-41 ac timing of input signal value signal symbol description min. typ. max. unit comment t dsmcf mlbsig and mlbdat input valid to mlbclk falling 4 ? ? ns mlbsig, mlbdat input t dhmcf mlbsig and mlbdat input hold from mlbclk low 0 ? ? ns 8.5.12.1.3. output signal table 8-42 ac timing of output signal value signal symbol description min. typ. max. unit comment t mcfdz mlbsig and mlbdat output high impedance from mlbclk low 0 ? t mckl ns mlbsig, mlbdat output t mdzh bus hold time 4 ? ? ns (*1) *1: the board must be designed to ensure that the high-impe dance bus does not leave the logic state of the final driven bit for this time period. therefore, coupling must be mi nimized while meeting the maximum capacitive load listed. 72 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.5.12.2. medialb ac spec type b ground = 0v, load capacitance = 40pf, medialb speed = 1024fs, and fs = 48khz. all timing parameters are specified fro m the valid voltage threshold as listed below; unless otherwise noted. 8.5.12.2.1. clock table 8-43 ac timing of clock signal value signal symbol description min. typ. max. unit comment f mck mlbclk operating frequency (*1) 45.056 ? ? ? 49.152 ? ? ? 49.2544 mhz 1024xfs at 44.0khz 1024xfs at 48.0khz 1024xfs at 48.1khz t mckr mlbclk rising time ? ? 1 ns v il to v ih t mckf mlbclk falling time ? ? 1 ns v ih to v il t mckc mlbclk cycle time ? 20.3 ? ns t mckl mlbclk low time 6.8 7.8 ? ns t mckh mlbclk high time 9.7 10.4 ? ns mlbclk t mpwv mlbclk pulse width variation ? ? 0.5 ns pp (*2) *1: the controller can shut off mlbclk to place medialb in a low-power state. *2: pulse width variation is measured at 1.25v by trigge ring on one edge of mlbclk and measuring the spread on the other edge, measured in ns peak-to-peak (pp). 8.5.12.2.2. input signal table 8-44 ac timing of input signal value signal name symbol description min. typ. max. unit comment t dsmcf mlbsig and mlbdat input valid to mlbclk falling 1 ? ? ns mlbsig, mlbdat input t dhmcf mlbsig and mlbdat input hold from mlbclk low 0 ? ? ns 8.5.12.2.3. output signal table 8-45 ac timing of output signal value signal name symbol description min. typ. max. unit comment t mcfdz mlbsig and mlbdat output high impedance from mlbclk low 0 ? t mckl ns mlbsig, mlbdat output t mdzh bus hold time 2 ? ? ns (*1) *1: the board must be designed to ensure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. therefore, coupling must be mini mized while meeting the maximum capacitive load listed. 73 fujitsu microelectronics proprietary and confidential MB86R01 data sheet figure 8-30 medialb timing figure 8-31 medialb pulse width variation timing 74 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.5.13. usb2.0 signal timing table 8-46 high-speed ac timing va l u e signal symbol description min. typ. max. unit driver characteristics: t hsr rise time (10% - 90%) 500 ? ? ps t hsf fall time (10% - 90%) 500 ? ? ps ? driver waveform requirements complying with usb2.0 specification (section 7.1.2) usb_hsdp usb_hsdm usb_fsdp usb_fsdm zhsdrv driver output resistance (which also serves as high- speed termination) 40.5 ? 49.5 ? clock timing: thsdrat high-speed data rate 479.760 ? 480.240 mb/s high-speed data timing: ? data source jitter ? receiver jitter tolerance complying with usb2.0 specification (section 7.1.2) table 8-47 full-speed ac timing va l u e signal symbol description min. typ. max. unit driver characteristics: t fr rise time (10% - 90%) 4 ? 20 ns t ff fall time (10% - 90%) 4 ? 20 ns t frfm difference rise and fall time matching 90 ? 111.11 % clock timing: (in case of using utmi i/f and setting fssel = "0") t fdraths full-speed data rate for hubs and devices which are capable of high-speed 11.9940 ? 12.0060 mb/s full-speed data timings: (in case of usi ng utmi i/f and setting fssel = "0") t dj1 t dj2 source jitter total (including frequency tolerance): to next transition for paired transitions -3.5 -4 ? ? 3.5 4 ns t fdeop source jitter for differential transition to se0 transition -2 ? 5 ns t jr1 t jr2 receiver jitter: to next transition for paired transitions -18.5 -9 ? 18.5 9 ns t feopt source se0 interval of eop 160 ? 175 ns t feopr receiver se0 interval of eop 82 ? ? ns usb_hsdp usb_hsdm usb_fsdp usb_fsdm t fst width of se0 interval during differential transition ? ? 14 ns table 8-48 low-speed ac timing value signal symbol description min. typ. max. unit driver characteristics: t lr rise time (10% - 90%) 75 ? 300 ns t lf fall time (10% - 90%) 75 ? 300 ns usb_hsdp usb_hsdm usb_fsdp usb_fsdm t lrfm rise and fall time matching 80 ? 125 % 75 fujitsu microelectronics proprietary and confidential MB86R01 data sheet rise time fall time 10% 10% 90% 90% differential data lines figure 8-32 data signal rise and fall time 76 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.5.14. ide66 signal timing 8.5.14.1. ide pio timing table 8-49 ac timing of register access value symbol description mode0 mode1 mode2 mode3 mode4 unit t0 cycle time (min.) 600 383 330 180 120 ns t1 address valid to ide_xdior/ide_xdiow setup (min.) 70 50 30 30 25 ns t2 ide_xdior/ide_xdiow pulse width 8 bit (min.) 290 290 290 80 70 ns t2i ide_xdior/ide_xdiow recovery time (min.) ? ? ? 70 25 ns t3 ide_xdiow data setup (min.) 60 45 30 30 20 ns t4 ide_xdiow data hold (min.) 30 20 15 10 10 ns t5 ide_xdior data setup (min.) 50 35 20 20 20 ns t6 ide_xdior data hold (min.) 5 5 5 5 5 ns t6z ide_xdior data tristate (max.) 30 30 30 30 30 ns t9 ide_xdior/ide_xdiow to address valid hold (min.) 20 15 10 10 10 ns trd read data valid to ide_diordy active (if ide_diordy initially low after ta) (min.) 0 0 0 0 0 ns ta ide_diordy setup time 35 35 35 35 35 ns tb ide_diordy pulse width (max.) 1250 1250 1250 1250 1250 ns tc ide_diordy assertion to release (max.) 5 5 5 5 5 ns table 8-50 ac timing of data access value symbol description mode0 mode1 mode2 mode3 mode4 unit t0 cycle time (min.) 600 383 240 180 120 ns t1 address valid to ide_xdior/ide_xdiow setup (min.) 70 50 30 30 25 ns t2 ide_xdior/ide_xdiow pulse width 8 bit (min.) 165 125 100 80 70 ns t2i ide_xdior/ide_xdiow recovery time (min.) ? ? ? 70 25 ns t3 ide_xdiow data setup (min.) 60 45 30 30 20 ns t4 ide_xdiow data hold (min.) 30 20 15 10 10 ns t5 ide_xdior data setup (min.) 50 35 20 20 20 ns t6 ide_xdior data hold (min.) 5 5 5 5 5 ns t6z ide_xdior data tristate (max.) 30 30 30 30 30 ns t9 ide_xdior/ide_xdiow to address valid hold (min.) 20 15 10 10 10 ns trd read data valid to ide_diordy active (if ide_diordy initially low after ta) (min.) 0 0 0 0 0 ns ta ide_diordy setup time 35 35 35 35 35 ns tb ide_diordy pulse width (max.) 1250 1250 1250 1250 1250 ns tc ide_diordy assertion to release (max.) 5 5 5 5 5 ns 77 fujitsu microelectronics proprietary and confidential MB86R01 data sheet ide_dd[15:0] (write data) ide_xdcs[1:0] ide_da[2:0] ide_xdior/ ide_xdiow t1 ide_diordy (no wait) data data ide_dd[15:0] (read data) valid ide_diordy (wait) t2 t9 t2i t a tc tc tb trd t5 t6 t6z t3 t4 t0 figure 8-33 pio access timing 78 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.5.14.2. ide ultra dma timing table 8-51 ac timing of ultra dma value mode0 mode1 mode2 mode3 mode4 symbol description min. max. min. max. min. max. min. max. min. max. unit t2cycletyp typical sustained average 2 cycle time 240 ? 160 ? 120 ? 90 ? 60 ? ns t2cycle 2 cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge to next falling edge of strobe) 230 ? 154 ? 115 ? 86 ? 57 ? ns tcycle cycle time allowing for asymmetry and clock variati ons (from strobe edge to strobe edge) 112 ? 73 ? 54 ? 39 ? 25 ? ns tdvs data valid setup time at sender (from data valid until strobe edge) 70 ? 48 ? 30 ? 20 ? 6.7 ? ns tdvh data valid setup time at sender (from strobe edge until data may become invalid) 6.2 ? 6.2 ? 6.2 ? 6.2 ? 6.2 ? ns tfs first strobe time (for device to first negatedstrobe from stop during data in burst) ? 230 ? 200 ? 170 ? 130 ? 120 ns tli limited interlock time 0 150 0 150 0 150 0 100 0 100 ns tmli interlock time with minimum 20 ? 20 ? 20 ? 20 ? 20 ? ns tui unlimited interlock time 0 ? 0 ? 0 ? 0 ? 0 ? ns taz maximum time allowed for output drivers to release (from asserted or negated) ? 10 ? 10 ? 10 ? 10 ? 10 ns tzah minimum delay time required for output 20 ? 20 ? 20 ? 20 ? 20 ? ns tzad drivers to assert or negate (from released) 0 ? 0 ? 0 ? 0 ? 0 ? ns tenv envelope time (from dmack- to stop and hdmardy- during data in burst initiation and from ide_xdddmack to stop during data out burst initiation) 20 70 20 70 20 70 20 55 20 55 ns trfs ready-to-final-strobe time (no strobe edges shall be sent this long after negation of dmardy) ? 75 ? 70 ? 60 ? 60 ? 60 ns trp minimum time to assert stop or negate ide_dmarq 160 ? 125 ? 100 ? 100 ? 100 ? ns tiordyz maximum time before releasing ide_diordy ? 20 ? 20 ? 20 ? 20 ? 20 ns tziordy minimum time before driving strobe 0 ? 0 ? 0 ? 0 ? 0 ? ns tack setup and hold times for dmack- (before assertion or negation) 20 ? 20 ? 20 ? 20 ? 20 ? ns tss time from strobe edge to negation of dmarq or assertion of stop (when sender terminates burst) 50 ? 50 ? 50 ? 50 ? 50 ? ns 79 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 80 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.5.15. sd signal timing 8.5.15.1. clock table 8-52 ac timing of clock signal value signal name symbol description min. typ. max. unit sd_clk t_clk sd_clk cycle ? ? 20.83 (*1) mhz *1: 20.83mhz for sd memory card and 20mhz for multimedia card (mmc) 8.5.15.2. input/output signal table 8-53 ac timi ng of data signal value signal name symbol description min. typ. max. unit td_dat output data delay (standard of sd_clk falling edge) -6.0 ? 3.0 ns ts_dat input data setup (standard of sd_clk rising edge) 13.0 ? ? ns sd_dat[3:0] th_dat input data hold (standard of sd_clk rising edge) 19.0 ? ? ns sd_clk sd_dat[3:0] td_dat td_dat t_sdclk figure 8-36 output timing to media sd_dat[3:0] sd_clk valid data ts_dat th_dat valid data ts_dat th_dat figure 8-37 input timing from media 81 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.5.16. etm9 trace port signal timing table 8-54 ac timing of trace signal value signal name symbol description min. typ. max. unit tctlsr tracectl setup time to risi ng edge of traceclk. 2 ? ? ns tctlhr tracectl hold time to risi ng edge of traceclk. 1 ? ? ns tctlsf tracectl setup time to fall ing edge of traceclk. 2 ? ? ns tracectl tctlhf tracectl hold time to fall ing edge of traceclk. 1 ? ? ns tdatasr tracedata setup time to ri sing edge of traceclk. 2 ? ? ns tdatahr tracedata hold time to risi ng edge of traceclk. 1 ? ? ns tdatasf tracedata setup time to fa lling edge of traceclk. 2 ? ? ns tracedata[3:0] tdatahf tracedata hold time to fal ling edge of traceclk. 1 ? ? ns traceclk tracectl tc t l s f [note] MB86R01 supports only half-rate clocking mode. tc t l h r tc t l hf tc t l s r tdatasf tdatahr tdatahf tdatasr tracedata[3:0] figure 8-38 trace signal timing 82 fujitsu microelectronics proprietary and confidential MB86R01 data sheet 8.5.17. exirc signal timing table 8-55 ac timing value signal name symbol description min. typ. max. unit int_a[3:0] t dw input data-width a ? ? ns the case that external interrupt input re quest is edge (rising edge and falling edge ), input data width (tdw) is regulated as follows. when level ("h" or "l") is selected as the re quest, it should be held until in terrupt process is completed. a indicates apb bus clock cycle. apb bus clk int_a[3:0] t dw figure 8-39 exirc timing |
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